QU80386EXTC33 Intel, QU80386EXTC33 Datasheet - Page 16

no-image

QU80386EXTC33

Manufacturer Part Number
QU80386EXTC33
Description
IC INT PROC 5V 33MHZ 132QFP
Manufacturer
Intel
Datasheet

Specifications of QU80386EXTC33

Processor Type
386EX
Features
32-bit, Extended Temp
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
863827

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
QU80386EXTC33
Manufacturer:
PROCONN
Quantity:
40 000
Part Number:
QU80386EXTC33
Manufacturer:
INTEL
Quantity:
10
Part Number:
QU80386EXTC33
Manufacturer:
FREESCALE
Quantity:
1 216
Part Number:
QU80386EXTC33
Manufacturer:
Intel
Quantity:
10 000
Part Number:
QU80386EXTC33
Manufacturer:
FREESCALE
Quantity:
1 216
Part Number:
QU80386EXTC33
Manufacturer:
INT
Quantity:
20 000
Intel386™ EX Embedded Microprocessor
16
Table 4.
Intel386™ EX Microprocessor Pin Descriptions (Sheet 4 of 6)
PWRDOWN
RD#
READY#
RESET
REFRESH#
RI1:0#
RTS1#
RTS0#
RXD1:0
SMI#
SMIACT#
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Symbol
Type
I/O
ST
ST
O
O
O
O
O
O
I
I
Output States
R(WH)
R(WL)
R(WL)
H(Q)
H(Z)
R(Z)
P(X)
H(X)
P(X)
H(X)
P(X)
P(X)
P(1)
H(1)
R(1)
P(1)
P(Z)
H(1)
R(1)
H(1)
R(1)
I(Q)
I(X)
I(1)
I(Z)
I(X)
I(X)
I(X)
Powerdown indicates that the processor is in powerdown mode.
PWRDOWN is multiplexed with P3.6.
Read Enable indicates that the current bus cycle is a read cycle.
Ready indicates that the current bus transaction has completed.
An external device or an internal signal can drive READY#.
Internally, the chip-select wait-state logic can generate the ready
signal and drive the READY# pin active.
Reset suspends any operation in progress and places the
processor into a known reset state.
Refresh indicates that the current bus cycle is a refresh cycle.
REFRESH# is multiplexed with CS6#.
Ring Indicator SIO1 and SIO0 indicate that the modem or data
set has received a telephone ringing signal. RI1# is multiplexed
with SSIORX, and RI0# is multiplexed with P1.4 and has a
temporary weak pull-up resistor.
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
RTS0# is multiplexed with P1.1.
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
RTS0# is multiplexed with P1.1.
Receive Data SIO1 and SIO0 accept serial data from the
modem or data set to the corresponding asynchronous serial
channel. RXD1 is multiplexed with DRQ1, and RXD0 is
multiplexed with P2.5 and has a temporary weak pull-down
resistor.
System Management Interrupt invokes System Management
Mode (SMM). SMI# is the highest priority external interrupt. It is
latched on its falling edge and forces the CPU into SMM upon
completion of the current instruction. SMI# is recognized on an
instruction boundary and at each iteration for repeat string
instructions. SMI# cannot interrupt LOCKed bus cycles or a
currently executing SMM. When the processor receives a
second SMI# while in SMM, it latches the second SMI# on the
SMI# falling edge. However, the processor must exit SMM by
executing a resume instruction (RSM) before it can service the
second SMI#. SMI# has a permanent weak pull-up resistor.
System Management Interrupt Active indicates that the
processor is operating in System Management Mode (SMM). It
is asserted when the processor initiates an SMM sequence and
remains asserted (LOW) until the processor executes the
resume instruction (RSM).
Name and Function
Datasheet

Related parts for QU80386EXTC33