RTPXA270C5C312 Intel, RTPXA270C5C312 Datasheet - Page 98

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RTPXA270C5C312

Manufacturer Part Number
RTPXA270C5C312
Description
IC MPU 32BIT 312MHZ 356-PBGA
Manufacturer
Intel
Datasheet

Specifications of RTPXA270C5C312

Processor Type
XScale®
Speed
312MHz
Voltage
1.25V
Mounting Type
Surface Mount
Package / Case
356-PBGA
For Use With
460-3472 - KIT DEV ZOOM STARTER FOR PXA270
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
868403

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Intel® PXA270 Processor
AC Timing Specifications
6-34
Symbols
tsramAS
tsramAH
tsramASW
tsramCES
tsramCEH
tsramWL
tsramDSWH
tsramDH
tramCD
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
2. On the first data beat of burst transfer, the tsramASW is 3 CLK_MEM periods. On subsequent data beats, the tsramASW is 1
loading and transition direction (rise or fall).
CLK_MEM period.
Table 6-19. SRAM Write AC Specification
Note:
During writes, data pins are actively driven by the processor and are not three-stated, regardless of
the states of the individual DQM signals. For SRAM writes, the DQM signals are used as byte
enables.
Table 6-19
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Parameters
Address setup to nCS assert
Address hold from nWE de-asserted
Address setup to nWE asserted
nCS setup to nWE asserted
nCS hold from nWE de-asserted
nWE asserted time
MD/DQM setup to nWE de-asserted
MD/DQM hold from nWE de-
asserted
nCS de-asserted after a read to next
nCS or nSDCS asserted (minimum)
lists programmable register items. See the “Memory Controller”chapter in the Intel®
MIN
1
1
1
2
1
1
2
1
1
Electrical, Mechanical, and Thermal Specification
MSCx[RRR]*2+
MSCx[RDN]+1
MSCx[RDN]+2
TYP
1
MAX
31
32
15
1
1
3
2
1
1
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
Units
1
Notes
2

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