ATF16V8CZ-12PC Atmel, ATF16V8CZ-12PC Datasheet - Page 7

• Manufacturer Part Number: ATF16V8CZ-12PC
• Description: IC PLD 12NS 20DIP
• Manufacturer: Atmel

Specifications of ATF16V8CZ-12PC

• Programmable Type: EE PLD
• Number Of Macrocells: 8
• Voltage - Input: 5V
• Speed: 12ns
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Family Name: ATF16V8CZ
• Process Technology: EECMOS
• # Macrocells: 8
• # I/os (max): 8
• Frequency (max): 83MHz
• Propagation Delay Time: 12ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Supply Current: 95mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATF16V8CZ12PC

4.5
4.6
5. Security Fuse Usage
0453H–PLD–7/05
Power-up Reset
Preload of Registered Outputs
The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly
from V
put state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
required:
The ATF16V8CZ’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by approved programmers.
A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Parameter
t
V
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the
3. The signals from which the clock is derived must remain stable during t
PR
RST
clock term high, and
CC
crossing V
CC
rise must be monotonic, from below 0.7V,
RST
Description
Power-up Reset Time
Power-up Reset Voltage
, all registers will be reset to the low state. As a result, the registered out-
CC
actually rises in the system, the following conditions are
Typ
600
3.8
ATF16V8CZ
1,000
Max
4.5
PR
.
Units
ns
V
7