ATF20V8BQ-10PC Atmel, ATF20V8BQ-10PC Datasheet - Page 6

• Manufacturer Part Number: ATF20V8BQ-10PC
• Description: IC PLD 8CELL QTR PWR 10NS 24DIP
• Manufacturer: Atmel

Specifications of ATF20V8BQ-10PC

• Programmable Type: EE PLD
• Number Of Macrocells: 8
• Voltage - Input: 5V
• Speed: 10ns
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Family Name: ATF20V8BQ
• Process Technology: CMOS
• # Macrocells: 8
• # I/os (max): 8
• Frequency (max): 83MHz
• Propagation Delay Time: 10ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V
ensures that all logic array inputs are at known states.
Input Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus com-
binatorial outputs and dedicated outputs versus outputs
with output enable control.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
6
ATF20V8B(Q)(L)
CC
. This
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
I/O Diagram
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessi-
ble regardless of the state of the security fuse.