ATF22LV10CZ-25SI Atmel, ATF22LV10CZ-25SI Datasheet - Page 6
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ATF22LV10CZ-25SI
Manufacturer Part Number
ATF22LV10CZ-25SI
Description
IC PLD EE 25NS 24-SOIC
Manufacturer
Atmel
Datasheet
1.ATF22LV10CZ-25SC.pdf
(19 pages)
Specifications of ATF22LV10CZ-25SI
Programmable Type
EE PLD
Number Of Macrocells
10
Voltage - Input
3.3V
Speed
25ns
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Family Name
ATF22LV10CZ
Process Technology
EECMOS
# Macrocells
10
# I/os (max)
10
Frequency (max)
40MHz
Propagation Delay Time
25ns
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.5V
Supply Current
90mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Package Type
SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATF22LV10CZ25SI
4.4
4.4.1
4.4.2
4.5
4.6
4.7
6
Input Test Waveforms
Input Test Waveforms and Measurement Levels
Output Test Loads
Note:
Pin Capacitance
Table 4-1.
Note:
Power-up Reset
The registers in the Atmel
from V
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
Preload of Register Outputs
The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
C
C
1. The V
2. The clock must remain stable during T
3. After T
Atmel ATF22LV10C(Q)Z
IN
I/O
CC
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
crossing V
CC
PR
Pin Capacitance (f = 1MHz, T = 25C
rise must be monotonic and start below 0.7V
, all input and feedback setup times must be met before driving the clock pin high
RST
Typ
CC
5
6
, all registers will be reset to the low state. The output state will depend on the polarity of the
actually rises in the system, the following conditions are required:
®
ATF22LV10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
Max
8
8
PR
(1)
Units
)
pF
pF
Conditions
V
V
OUT
IN
= 0V
= 0V
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