CS42L52-CNZ Cirrus Logic Inc, CS42L52-CNZ Datasheet - Page 36

• Manufacturer Part Number: CS42L52-CNZ
• Description: IC CODEC STER HDPN & SPKR 40QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L52-CNZ

• Package / Case: 40-QFN
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 98
• Voltage - Supply, Analog: 1.65 V ~ 2.63 V
• Voltage - Supply, Digital: 1.65 V ~ 2.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Package: 40QFN EP
• Adc/dac Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Number Of Dacs: 2
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1628

36
4.7
4.7.1
LRCK
SCLK
SDIN
LRCK
SCLK
SDOUT
SDIN
SDOUT
LRCK
SCLK
SDIN
LRCK
SCLK
SDIN
Digital Interface Formats
The serial port operates in standard I²S, Left-justified, Right-justified (DAC only), or DSP Mode digital inter-
face formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the
rising edge of SCLK.
DSP Mode
In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edge after the frame sync
rising edge. The right channel immediately follows the left channel.
M S B
L S B
M S B
M S B
AOUTA / AINxA
AOUTA / AINxA
L eft C h a n n el
L e f t C h a n n e l
L eft C h a n n el
Audio Word Length (AWL)
Figure 18. Right-Justified Format (DAC only)
M S B
L eft C h a n n el
HP/LINE OUTA
Audio W ord Length (AW L)
Figure 17. Left-Justified Format
Figure 19. DSP Mode Format)
AO UTL
Figure 16. I²S Format
L S B
L S B
5/13/08
L S B
M S B
L S B
1/fs
M S B
M S B
AOUTB / AINxB
AOUTB / AINxB
R ig ht C h a n n el
R ig ht C h a n n el
R ig ht C h a n n el
HP/LINE OUTB
R i g h t C h a n n e l
M S B
AO UTR
L S B
L S B
CS42L52
L S B M S B
MSB
DS680F1
L S B
MSB