CS42L55-CNZ Cirrus Logic Inc, CS42L55-CNZ Datasheet - Page 44

• Manufacturer Part Number: CS42L55-CNZ
• Description: IC CODEC STER H-HDPN AMP 36QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L55-CNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 99
• Voltage - Supply, Analog: 1.65 V ~ 2.71 V
• Voltage - Supply, Digital: 1.65 V ~ 2.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 48kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1506 - BOARD EVAL FOR CS42L55 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1629

44
6.4.3
6.4.4
6.4.5
6.5
6.5.1
Reserved
7
Clocking Control 2 (Address 05h)
SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
MCLK Divide By 2
Configures a divide of the input MCLK prior to all internal circuitry.
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
Note:
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
Notes:
1. Slave/Master Mode is determined by the M/S bit in
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
SCK=MCK[1:0]
00
01
10
11
MCLKDIV2
0
1
Application:
MCLKDIS
0
1
SPEED[1:0]
00
01
10
11
Application:
(“32 kHz Sample Rate Group” on page
page
Refer to the referenced application for more information.
Reserved
This function should be enabled during power down (PDN=1) ONLY.
45). Low sample rates may also affect dynamic range performance in the typical audio band.
6
Output SCLK
Re-timed, bursted signal with minimal speed needed to clock the required data samples
Reserved
MCLK signal after the MCLK divide (MCLKDIV2) circuit
MCLK signal before the MCLK divide (MCLKDIV2) circuit
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
MCLK signal into CODEC
On
Off; Disables the clock tree to save power when the CODEC is powered down.
Serial Port Speed
Reserved
Single-Speed Mode (SSM)
Half-Speed Mode (HSM)
Quarter-Speed Mode (QSM)
“Serial Port Clocking” on page 34
Reserved
5
SPEED1
4
45) and the RATIO[1:0] bits
SPEED0
3
“Master/Slave Mode” on page
32kGROUP
2
(“Internal MCLK/LRCK Ratio” on
RATIO1
1
43.
CS42L55
RATIO0
DS773F1
0