CS42416-CQZ Cirrus Logic Inc, CS42416-CQZ Datasheet - Page 24
![IC CODEC 6CH 110DB 192KHZ 64LQFP](/photos/6/80/68054/cs42416-cqz_sml.jpg)
CS42416-CQZ
Manufacturer Part Number
CS42416-CQZ
Description
IC CODEC 6CH 110DB 192KHZ 64LQFP
Manufacturer
Cirrus Logic Inc
Type
General Purposer
Datasheet
1.CS42416-CQZ.pdf
(73 pages)
Specifications of CS42416-CQZ
Package / Case
64-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 6
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 110
Voltage - Supply, Analog
4.75 V ~ 5 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
2
Number Of Dac Outputs
6
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/6 DAC
Thd Plus Noise
- 100 dB ADC / - 100 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1028
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24
4.4.2
4.4.3
4.4.4
OMCK System Clock Mode
A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be
used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register
trol (address 06h)” on page
ter clock functionality. The clock auto-switching mode allows the clock input through OMCK to be used as
a clock in the system without any disruption when the PLL loses lock, for example, when the LRCK is re-
moved from ADC_LRCK. This clock-switching is done glitch-free. A clock adhering to the specifications
detailed in the Switching Characteristics table on
that the FRC_PLL_LK bit is set to ‘0’ (See
Master Mode
In Master Mode, the serial interface timings are derived from an external clock attached to OMCK or from
the output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 bits in the Clock Control
Register (See
Slave Mode
In Slave Mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the
supplied master clock, OMCK, or must be synchronous to the supplied ADC_LRCK used as the input to
the PLL. In this latter scenario, the PLL output becomes the internal master clock. The supported PLL out-
put frequencies are shown in
The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronous to the corresponding
DAC_LRCK/ADC_LRCK and be equal to 128x, 64x, 48x or 32x Fs, depending on the interface format se-
lected and desired speed mode.
Sample
(kHz)
Rate
192
48
96
12.2880 18.4320 24.5760
256x
Sample
“Clock Control (address 06h)” on page
(kHz)
176.4
Rate
-
-
44.1
88.2
192
32
48
64
96
Single-Speed
(4 to 50 kHz)
384x
-
-
Single-Speed
(4 to 50kHz)
Table 1. Common OMCK Clock Frequencies
48. An advanced auto-switching mode is also implemented to maintain mas-
12.2880
11.2896
8.1920
256x
Table
512x
-
-
-
-
-
-
-
2.
12.2880 18.4320 24.5760
128x
PLL Output (MHz)
-
-
“Force PLL Lock (FRC_PLL_LK)” on page
Double-Speed
(50 to 100kHz)
(50 to 100 kHz)
Double-Speed
OMCK (MHz)
16.3840
22.5792
24.5760
256x
192x
page 11
-
-
-
-
-
-
-
48).
256x
must be applied to the OMCK pin at all times
-
-
(100 to 192kHz)
Quad-Speed
12.2880 18.4320 24.5760
45.1584
49.1520
64x
256x
-
-
(100 to 192 kHz)
-
-
-
-
-
-
Quad-Speed
96x
-
-
128x
49).
-
-
CS42416
“Clock Con-
DS602F1