XE3005I064TRLF Semtech, XE3005I064TRLF Datasheet - Page 14

• Manufacturer Part Number: XE3005I064TRLF
• Description: IC CODEC LOW PWR 16BIT 20-UCSP
• Manufacturer: Semtech
• Type: Audio Codecr

Specifications of XE3005I064TRLF

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 78 / 78
• Dynamic Range, Adcs / Dacs (db) Typ: 78 / 78
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-UCSP®
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: XE3005I064TR

SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling edge of
BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the
BLCK. Each rising edge of the FSYNC indicates the start of a new sample.
3.1.1
For transmitting and receiving, 32 clock cycles in one frame are always required (figure 12 and 13). This is even the case
when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and microcontroller.
If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be shortened).
In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the data is
transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.
Note! This optimization is possible in slave mode only.
The figure 15 shows this special LFS mode.
3.2
The control registers define the configuration of the CODEC and define the various modes of operation. During power-up,
all registers will be configured with default values. The control register set consists of 16 registers. A detailed description
is provided chapter 7.
The control registers can be changed in the two following ways:
There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI
during the power up startup sequence as described in section 2.1.10
© Semtech 2005
1. Logic values at SPI pins during power-up
REGISTER PROGRAMMING
LFS Optimization
FSYNC
BCLK
Value at power up
SDO
SDI
MOSI = 0
MOSI = 1
SCK = 0
SCK = 1
Figure 15: Audio interface timing in LFS mode, 17 BLCK cycles, channel 2
SS = 1
SS = 0
channel 1, no data
-
-
msb
n
n
15
15
Influenced bits of registers
Register I(0)=0
Register I(0)=1
Register J(0)=1
Register J(0)=0
Register E(2) = 0
Register E(2) = 1
n
n
14
14
channel 2, sample n
14
channel 1, no data
lsb
n
n
0
0
-
-
msb
channel 2, sample n+1
n
comments
MCLKDIV division by 1
MCLKDIV division by 2
SFS protocol
LFS protocol
preamplifier gain x5
preamplifier gain x20
n
15
15
n
n
14
14
XE3005/XE3006
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