TP3070V-G/NOPB National Semiconductor, TP3070V-G/NOPB Datasheet - Page 13
![IC INTERFAC PCM COMBO II 28-PLCC](/photos/6/58/65877/v28a_sml.jpg)
TP3070V-G/NOPB
Manufacturer Part Number
TP3070V-G/NOPB
Description
IC INTERFAC PCM COMBO II 28-PLCC
Manufacturer
National Semiconductor
Series
COMBO®IIr
Type
PCM Codec/Filterr
Datasheet
1.TP3070V-GNOPB.pdf
(26 pages)
Specifications of TP3070V-G/NOPB
Data Interface
PCM Audio Interface
Number Of Adcs / Dacs
1 / 1
Sigma Delta
No
Voltage - Supply, Analog
±5V
Voltage - Supply, Digital
±5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*TP3070V-G
*TP3070V-G/NOPB
TP3070V-G
*TP3070V-G/NOPB
TP3070V-G
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TP3070V-G/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
PCM INTERFACE TIMING
t
t
t
t
t
t
SERIAL CONTROL PORT TIMING
f
t
t
t
t
t
t
t
t
t
t
t
Symbol
DBZ
DBT
ZBT
DFD
SDB
HBD
CCLK
WCH
WCL
RC
FC
HCS
HSC
SSC
SSCO
SDC
HCD
DCD
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at T
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
specified at V
All timing parameters are measured at V
See Definitions and Timing Conventions section for test methods information.
Timing Specifications
Delay Time, BCLK Low to D
Disabled if FS
D
Low, or BCLK High to D
Disabled if FS
Delay Time, BCLK High to TS
Low if FS
TS
Delayed Mode); BCLK High to
TS
TRI-STATE Time, BCLK Low to
TS
to TS
BCLK High to TS
High
Delay Time, FS
High to Data Valid
Setup Time, D
Valid to BCLK Low
Hold Time, BCLK
Low to D
Frequency of CCLK
Period of CCLK High
Period of CCLK Low
Rise Time of CCLK
Fall Time of CCLK
Hold Time, CCLK Low
to CS Low
Hold Time, CCLK
Low to CS High
Setup Time, CS
Transition to CCLK Low
Setup Time, CS
Transition to CCLK High
Setup Time, CI (CI/O)
Data In to CCLK Low
Hold Time, CCLK
Low to CI/O Invalid
Delay Time, CCLK High
to CI/O Data Out Valid
X
0/1 disabled if 8th BCLK
X
X
X
CC
Low if BCLK High (Non
Low (Delayed Data Mode)
High if FS
X
= +5V, V
High if 8th BCLK Low, or
R
X
0/1 Invalid
Parameter
High, or FS
X
X
R
X
BB
X/R
0/1
Low, FS
High
Low, FS
X
= −5V, T
High if FS
X
X
X
High to
X
0/1
Low to
Low
(Continued)
A
X
X
0/1
= 25˚C.
X
OH
= 2.0V and V
D
or V
Figure 5
−40˚C to +85˚C (TP3070-X)
Load = 100 pF Plus 2 LSTTL Loads
Load = 100 pF Plus 2 LSTTL Loads,
Applies if FS
BCLK Rising Edge in Non-Delayed
Data Mode Only
−40˚C to +85˚C (TP3070-X)
−40˚C to +85˚C (TP3070-X)
Measured from V
Measured from V
Measured from V
Measured from V
CCLK1
CCLK 8
Load = 100 pF plus 2 LSTTL Loads
−40˚C to +85˚C (TP3070-X)
X
0/1 Disabled is measured at V
OH
according to Figure 4 or
OL
X/R
Conditions
= 0.7V.
Rises Later than
13
IH
IL
IL
IH
to V
to V
to V
to V
IL
IH
IH
IL
OL
CC
= +5V
A
= 25˚C. All other limits are assured by
Min
160
160
100
15
15
15
30
15
15
10
60
50
50
50
±
5%; V
Typ
BB
= −5V
2048
Max
100
100
80
60
60
80
90
50
50
80
±
5%; T
A
www.national.com
= 0˚C to
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns