MAX9867EWV+T Maxim Integrated Products, MAX9867EWV+T Datasheet - Page 25

• Manufacturer Part Number: MAX9867EWV+T
• Description: IC STEREO AUD CODEC LP 30WLP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867EWV+T

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-WLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX9867EWV+T; MAX9867EWV+TTR

Table 4. Clock Control Registers (continued)
Table 5. Common NI Values
Note: Bolded values are exact integers that provide maximum full-scale performance.
MCLK (MHz)
11.2896
12.288
19.2
FREQ
BITS
12
13
24
26
27
PLL
NI
Exact Integer Modes
Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.
Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio
cannot be guaranteed, use PLL mode instead.
PLL Mode Enable
0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the
1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock Mode
To enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.
Normal Mode LRCLK Divider
When PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.
NI = (65536 x 96 x f
f
f
LRCLK > 24kHz is only valid for MODE = 0 (stereo audio mode). MODE = 1 (voice mode) requires LRCLK ≤
24kHz.
______________________________________________________________________________________
LRCLK
PCLK
PSCLK
MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an
LRCLK as specified by the divide ratio.
01
01
01
01
01
10
10
10
= Prescaled MCLK internal clock frequency (PCLK)
= LRCLK frequency
FREQ[3:0]
0x1–0x7
Ultra-Low Power Stereo Audio Codec
0x00
0xA
0xB
0xC
0xD
0xE
0xF
0x8
0x9
0x0A3D
LRCLK
0x116A
0x1062
0x1000
0x0F20
0x1062
0x0F20
0x0E90
8
)/f
PCLK
PCLK (MHz)
0x22D4
0x20C5
0x20C5
0x1D21
0x2000
0x1E3F
0x147B
0x1E3F
Reserved
16
19.2
19.2
12
12
13
13
16
16
LRCLK (kHz)
FUNCTION
0x2D5F
0x1EB8
0x15D8
0x343F
0x3127
0x3000
0x1893
0x16AF
24
Normal or PLL mode
LRCLK (kHz)
Reserved
0x3C7F
0x3C7F
0x45A9
0x4000
0x3A41
0x4189
0x28F6
0x4189
16
16
16
16
8
8
8
8
32
0x6000
0x5A51
0x5833
0x535F
0x3873
0x5A51
0x535F
0x5048
44.1
PCLK/LRCLK
Reserved
812.5
1500
1625
2000
1000
2400
1200
750
0x687D
0x5ABE
0x3D71
0x5ABE
0x624E
0x6000
0x624E
0x5762
48
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