CS4299-BQZ Cirrus Logic Inc, CS4299-BQZ Datasheet - Page 27

• Manufacturer Part Number: CS4299-BQZ
• Description: IC CODEC AC'97 W/SRC 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Series: SoundFusion™r
• Type: Audio Codec '97r

Specifications of CS4299-BQZ

• Data Interface: Serial
• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 8
• No. Of Output Channels: 3
• Adc / Dac Resolution: 20bit
• Sampling Rate: 48kSPS
• Ic Interface Type: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS319PP6
4.13
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
Default
The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4299 as well as external am-
plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec-
tion of the CS4299 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must
be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the
powerdown functions.
EAPD
D15
Powerdown Control/Status Register (Index 26h)
PR6
D14
PR5
D13
down external amplifiers.
sections of the CS4299. The only way to recover from setting this bit is through a Cold Reset
(driving the RESET# signal active).
be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET#
signal (primary audio codec only).
powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before
writing any mixer registers.
reference is still active). When clearing this bit, the ANL bit should be checked before writing
any mixer registers.
DAC bit should be checked before sending any data to the DACs.
ered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit
goes high.
level.
trols are ready. When clear, no volume control registers should be written.
When clear, the DACs will not accept any valid data.
clear, no data will be sent to the Controller.
CS4299 finishes an initialization and calibration sequence.
External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power
Alternate Line Out Powerdown. When ‘set’, the alternate line out buffer is powered down.
Internal Clock Disable. When ‘set’, this bit completely powers down both the analog and digital
AC-link Powerdown. When ‘set’, the AC link is powered down (BIT_CLK off). The AC-link can
Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are
Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the voltage
Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the
L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are pow-
Voltage Reference Ready Status. When ‘set’, indicates the voltage reference is at a nominal
Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-
Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC link.
L/R ADC Ready Status. When ‘set’, the ADCs are ready to send data across the AC link. When
0000h. This value indicates all blocks are powered on. The lower four bits will change as the
PR4
D12
PR3
D11
D10
PR2
PR1
D9
PR0
D8
D7
0
D6
0
D5
0
D4
0
REF
D3
ANL
D2
CS4299
DAC
D1
CS4299
ADC
D0
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