IDTSTAC9752AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9752AXNAED1XR Datasheet - Page 36
![IC CODEC AC'97 MIC/JACK 32-QFN](/photos/6/56/65621/32-qfn_pkg_sml.jpg)
IDTSTAC9752AXNAED1XR
Manufacturer Part Number
IDTSTAC9752AXNAED1XR
Description
IC CODEC AC'97 MIC/JACK 32-QFN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec '97r
Datasheet
1.IDTSTAC9752AXNAED1XR.pdf
(106 pages)
Specifications of IDTSTAC9752AXNAED1XR
Resolution (bits)
20 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
85 / 92
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
STAC9752AXNAED1XR
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IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
5.3.1.
valid time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot
with 0s.
As an example, consider an 8-bit sample stream that is being played out to one of the STAC9752A/
9753A DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next
12 bit-positions which are stuffed with 0s by the AC‘97 Controller. This ensures that regardless of the
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC‘97 Controller it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
Slot 0: TAG / CODEC ID
S D A T A _ O U T
12-3
Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
1-0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
B I T _ C L K
E n d o f p r e v i o u s a u d i o f r a m e
S Y N C
2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)
Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)
a s s e r t e d
S Y N C
Slot 5: Modem Line 1 (not used on STAC9752A/9753A)
Table 7. Output Slot 0 Bit Definitions
36
Slot 8: Alternative PCM2 Right
Slot 9: Alternative PCM1 Right
Slot 6: Alternative PCM1 Left
Slot 7: Alternative PCM2 Left
d e t e c t e d b y
Slot 4: PCM Right channel
Slot 3: PCM Left channel
Slot 3-12 Valid Data bits
S Y N C
Slot 11: SPDIF Right
c o d e c
Slot 12: Audio GPIO
Reserved (Set to 0)
Slot 10: SPDIF Left
F r a m e
Description
Frame Valid
v a l i d
s l o t 1
S D A T A _ O U T
b i t o f f r a m e
STAC9752A/9753A
f i r s t
s l o t 2
PC AUDIO
V 1.5 1206
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