IDTSTAC9751XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9751XXTAEC1XR Datasheet - Page 54

• Manufacturer Part Number: IDTSTAC9751XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9751XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9751XXTAEC1XR

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
6.5.26.
6.5.27.
EAPD
EN15
D15
D15
EN7
D7
D7
GPIO Access Register (74h)
Default: 0800h
The GPIO Access Register requires that the output enable bits (D11, D9 and D8) be used in con-
junction with the data source selection (input or output) for the EAPD, GPIO0 and GPIO1 (pins 47,
43 and 44 respectively). For example, to use GPIO1 as an output, set D9 = 1 to enable the output,
and use D13 to write the output value desired. To use GPIO1 as an input, set D9 = 0 to disable the
output, and use D13 to read the input value.
High Pass Filter Bypass (Index 76h and 78h)
The High Pass Filter Bypass register (index 78h) is a locked register and can only be properly written
and read from when ABBAh has been written into register 76h. Bit D0 controls the High Pass Filter
Bypass. Default is zero which provides for normal operation where the high pass filter is active. Writ-
ing a one, will disable, or bypass the ADC high pass filter.
6.5.27.1. 78h Enable (76h)
Default: 0000h
Bit(s)
7:0
15
14
13
12
10
11
9
8
Reserved
EN14
EN6
D14
D14
D6
D6
Reset Value
0
0
0
0
1
0
0
0
0
GPIO1
EN13
EN5
D13
D13
D5
D5
Table 39. GPIO Access Registers (74h)
GPIO1_OEN
GPIO0_OEN
EAPD_OEN
Reserved
Reserved
Reserved
GPIO1
GPIO0
Name
EAPD
GPIO0
EN12
EN4
D12
D12
54
D4
D4
Reserved
EAPD data output on EAPD when bit D11 = 1
EAPD data input from pin when bit D11 = 0
Reserved
GPIO1 data output on GPIO1 when bit D9 = 1
GPIO1 data input from pin when bit D9 = 0
GPIO0 data output on GPIO0 when bit D8 = 1
GPIO0 data input from pin when bit D8 = 0
0 = EAPD data out disabled
1 = EAPD data output enabled
Reserved
0 = GPIO1 data out disabled
1 = GPIO1 data output enabled
0 = GPIO0 data out disabled
1 = GPIO0 data output enabled
Reserved
EAPD_OEN
EN11
EN3
D11
D11
D3
D3
Reserved
STAC9750/9751
EN10
EN2
D10
D10
D2
D2
Description
GPIO1_OEN GPIO0_OEN
EN9
EN1
D9
D1
D9
D1
PC AUDIO
V 5.8 103106
EN8
EN0
D8
D0
D8
D0