W681310WG Nuvoton Technology Corporation of America, W681310WG Datasheet - Page 7

• Manufacturer Part Number: W681310WG
• Description: IC VOICEBND CODEC 3V 1CH 20TSSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W681310WG

• Data Interface: PCM Audio Interface
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 2.7 V ~ 5.25 V
• Voltage - Supply, Digital: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: W681360DK - KIT DEVELOPMENT FOR W681360
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Pin
Name
V
RO-
PAI
PAO-
PAO+
V
FSR
PCMR
BCLKR
PUI
MCLK
BCLKT
PCMT
FST
V
μ/A-Law
AO
AI-
AI+
V
REF
DD
SS
AG
6. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
No.
Functionality
This pin is used to bypass the on-chip V
through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin.
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 0.886
volt peak referenced to the analog ground level.
This pin is the inverting input to the power amplifier. Its DC level is at the V
Inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially to
1.772 volt peak referenced to the V
Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially
to 1.772 volt peak referenced to the V
Power supply. This pin should be decoupled to V
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to V
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
Power up input signal. When this pin is tied to V
the part is powered down.
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended
to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in
the case of 256 and 512 kHz frequency.
PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI
mode and 256 kHz to 4800kHz in all other PCM modes.
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
This is the supply ground. This pin should be connected to 0V.
Compander mode select pin. μ-Law companding is selected when this pin is tied to V
companding is selected when this pin is tied to V
Analog output of the first gain stage in the transmit path.
Inverting input of the first gain stage in the transmit path.
Non-inverting input of the first gain stage in the transmit path.
Mid-Supply analog ground pin, which supplies a V
signal processing. This pin should be decoupled to V
becomes high impedance when the chip is powered down.
SS
- 7 -
AG
. The IDL mode is selected when this pin is tied to V
AG
voltage level.
DD
voltage level.
/2 voltage reference. It needs to be decoupled to V
DD
SS
SS
, the part is powered up. When tied to V
DD
.
with a 0.1μF ceramic capacitor.
/2 volt reference voltage for all-analog
SS
Publication Release Date: April 2007
with a 0.01μF capacitor. This pin
W681310
AG
Revision B14
voltage.
DD
. A-Law
DD
.
SS
,
SS