IDTSTAC9766XXTAEC1X IDT, Integrated Device Technology Inc, IDTSTAC9766XXTAEC1X Datasheet - Page 33

• Manufacturer Part Number: IDTSTAC9766XXTAEC1X
• Description: IC CODEC AC'97 2CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9766XXTAEC1X

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9766XXTAEC1X

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
5.3.3.
5.3.4.
5.3.5.
The control interface architecture supports up to 64 16-bit read/write registers, addressable on even
byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd registers (01h,
03h, etc.) are reserved for future expansion.
Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the
implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless
required to be readable as well as writeable to provide more robust testability.
AC-link output frame slot 1 communicates control register address, and write/read command infor-
mation to the STAC9766/9767.
The first bit (MSB) sampled by AC‘97 indicates whether the current control transaction is a read or a
write operation. The following 7 bit positions communicate the targeted control register address. The
trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC‘97 Control-
ler.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the cur-
rent command port operation is a write cycle. (as indicated by Slot 1, bit 19)
If the current command port operation is a read, then the entire slot time must be stuffed with 0 by
the AC‘97 Controller.
Slot 3: PCM Playback Left Channel
AC-link output frame slot 3 is the composite digital audio left playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-
olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-
tions within this time slot with 0.
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 4: PCM Playback Right Channel
AC-link output frame slot 4 is the composite digital audio right playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-
18:12
• Bit(19:4)
• Bit(3:0)
11:0
Bit
19
Read/Write command
Control Register Index
Reserved
Control Register Write Data
Description
Table 8. Command Address Port Bit Assignments
Reserved
33
1 = read, 0 = write
Sixty-four 16-bit locations, addressed on even byte boundaries
Stuffed with 0s
(Stuffed with 0 if current operation is a read)
(Stuffed with 0)
STAC9766/9767
Comments
PC AUDIO
V 7.4 12/06