IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 21

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
3.2
below:
1. Apply ground first;
2. Apply VCC, finish signal connections and set the RESET pin to logic
3. Set the RESET pin to logic high;
4. Select master clock frequency;
5. Program filter coefficients and other parameters as required;
3.3
by setting the RESET pin to logic low for at least 50
enter the default state as follows:
1. All four channels are powered down and in standby mode.
2. All loopbacks and cutoff are disabled.
3. The DX1 pin is selected for all channels to transmit data and the DR1
To power on the IDT821054, users should follow the sequence
low. The device then goes into the default state;
When the IDT821054 is powered on, or reset either by command or
pin is selected for all channels to receive data.
POWER-ON SEQUENCE
DEFAULT STATE AFTER RESET
µ
s, the device will
21
4. The master clock frequency is 2.048 MHz.
5. Transmit and receive time slots are set to be 0-3 respectively for
6. A-Law is selected.
7. The digital filters including GRX, FRR, GTX, FRX, GIS, ECF and IMF
8. The SB1, SB2 and SB3 pins are configured as inputs.
9. The SI1 and SI2 pins are configured as no debounce.
10.All interrupts are disabled and all pending interrupts are cleared.
11. All feature function blocks including FSK generator, dual tone
12.The outputs of CHCLK1 and CHCLK2 are set to high.
operations. So the RAM data will not be lost unless the device is
powered down physically.
Channel 1-4. The PCM data rate is as same as the BCLK frequency.
The PCM data is transmitted on rising edges of the BCLK signal and
received on falling edges of it.
are disabled. The high-pass filters (HPF) are enabled. Refer to
Figure - 4
generators, hardware ring trip and level meter are disabled.
The data stored in the RAM will not be changed by any kind of reset
and descriptions on LREG1 for details.
INDUSTRIAL TEMPERATURE RANGE