EMC1414-1-AIZL-TR SMSC, EMC1414-1-AIZL-TR Datasheet - Page 40

• Manufacturer Part Number: EMC1414-1-AIZL-TR
• Description: Board Mount Temperature Sensors SMBus Temp Sensor Selectable Address
• Manufacturer: SMSC

Specifications of EMC1414-1-AIZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADDR.
35h
ADDR.
APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When
Revision 1.38 (09-30-10)
36h
7.15
7.16
SETTING
R/W
R-C
12h
13h
14h
15h
16h
17h
R/W
R-C
The High Limit Status Register contains the status bits that are set when a temperature channel high
limit is exceeded. If any of these bits are set, then the HIGH status bit in the Status Register is set.
Reading from the High Limit Status Register will clear all bits if. Reading from the register will also
clear the HIGH status bit in the Status Register.
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and
any of these status bits are set.
The status bits will remain set until read unless the ALERT pin is configured as a comparator output
(see
Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel exceeds its programmed high limit.
Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high limit.
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
The Low Limit Status Register contains the status bits that are set when a temperature channel drops
below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set.
Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear
the LOW status bit in the Status Register.
High Limit Status Register
Low Limit Status Register
Table 7.19 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued)
REGISTER
High Limit
Status
Section
REGISTER
Low Limit
Status
measuring a 45nm Intel CPU, the Ideality Setting should be 15h.
FACTOR
1.0000
1.0013
1.0026
1.0039
1.0053
1.0066
6.3.2).
B7
-
B7
-
Table 7.20 High Limit Status Register
Table 7.21 Low Limit Status Register
B6
-
B6
SETTING
-
22h
23h
24h
25h
26h
27h
B5
DATASHEET
-
B5
-
Multiple Channel 1°C Temperature Sensor with Beta Compensation
40
B4
-
B4
-
FACTOR
1.0213
1.0226
1.0239
1.0252
1.0265
1.0278
E3HIGH
E3LOW
B3
B3
E2LOW
E2HIGH
B2
B2
SETTING
32h
33h
34h
35h
36h
37h
E1LOW
E1HIGH
B1
B1
SMSC EMC1413/EMC1414
ILOW
IHIGH
B0
B0
FACTOR
1.0421
1.0434
1.0447
1.0460
1.0473
1.0486
Datasheet
DEFAULT
DEFAULT
00h
00h