EMC2300-AZC-TR SMSC, EMC2300-AZC-TR Datasheet - Page 69

• Manufacturer Part Number: EMC2300-AZC-TR
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC2300-AZC-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
SMSC EMC2300
8.2.23
Register
Address
BIT
0
1
2
3
4
5
6
7
80h
Reserved
SUREN
NAME
P2INT
SMSC
SMSC
Read/
T3INT
TRDY
Write
R/W
INIT
This register contains the following bits:
Register 80h: Interrupt Enable 2 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),
which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
See
This register contains the following bits:
Figure 6.1 Interrupt Control on page
Interrupt Enable 2 (Fan
Register Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Tachs)
Table 8.44 Register 80h: Interrupt Enable 2 Register
DEFAULT
Table 8.43 Configuration Register Bits
0
0
0
0
1
0
0
0
Determines functionality of the TACH3/INT# pin.
Determines the functionality of the PWM2/INT# pin.
Reserved
Temperature Reading Ready - indicates that the temperature reading
registers hold valid values.
Spin-up reduction enable - when set, this bit enables the reduction of the
spin-up time based on feedback from all fan tachometers associated with
each PWM.
SMSC - Writing to this bit to a value different from the default value may
cause unwanted results.
SMSC - Writing this bit to a value different than the default value may
cause unwanted results.
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing.
Soft Reset sets all the registers except the Reading Registers to their
default values.
(MSb)
Bit 7
RES
‘0’ - TACH3 input
‘1’- INT# output
‘0’ - PWM2 output.
‘1’ - INT# output.
DATASHEET
Bit 6
RES
24.
69
Bit 5
RES
TACH4
Bit 4
DESCRIPTION
TACH3
Bit 3
TACH2
Bit 2
TACH1
Bit 1
Revision 0.32 (06-23-08)
TACH
(LSb)
Bit 0
Default
Value
1Eh