EMC6D102-CZC SMSC, EMC6D102-CZC Datasheet - Page 47

• Manufacturer Part Number: EMC6D102-CZC
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC6D102-CZC

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
99-FEh
7.1
Addr
Reg
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
FFh
87h
88h
89h
90h
91h
92h
93h
94h
95h
96h
97h
98h
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Undefined Registers
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted
Note 7.1
Note 7.2
Note 7.3
Note 7.4
Note 7.5
Note 7.6
Note 7.7
The registers shown in the table above are the defined registers in the part. Any reads to undefined
registers always return 00h. Writes to undefined registers have no effect and do not return an error.
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
PWM1 Option
PWM2 Option
PWM3 Option
Tach1 Option
Tach2 Option
Tach3 Option
Tach4 Option
Reg Name
Reserved
Reserved
results.
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in
manual mode. In this case, the register is writable when the start bit is set, but not when
the lock bit is set.
The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The
OVRID bit is always writable, both when the start bit is set and when the lock bit is set.
The Interrupt status registers are cleared on a read if no events are active
The INTEN bit in register 7Ch is always writable, both when the start bit is set and when
the lock bit is set.
In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not
accessible except for the following: Bits[2:0] in the Special Function Register (SFTR) at
offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh.
These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the
hardware.
SMSC bits may be read/write bits. Writing these bits to a value other than the default value
may cause unwanted results
Table 7.1 Register Summary (continued)
Note 7.6
Note 7.6
Note 7.6
STCH2
STCH2
STCH2
STCH2
VCC.3
V50.3
MSb
TST7
TST7
TST7
TST7
TST7
Bit 7
RES
RES
RES
RES
RES
RES
RES
RES
RES
Note 7.6
Note 7.6
Note 7.6
STCH1
STCH1
STCH1
STCH1
VCC.2
TST 6
TST 6
TST 6
V50.2
TST6
TST6
TST6
TST6
DATASHEET
Bit 6
RES
RES
RES
RES
RES
RES
RES
STCH0
STCH0
STCH0
STCH0
VCC.1
V50.1
TST 5
TST 5
TST 5
TST5
TST5
TST5
TST5
Bit 5
RES
RES
RES
OPP
OPP
OPP
RES
47
VCC.0
3EDG
3EDG
3EDG
3EDG
GRD1
GRD1
GRD1
TST 4
TST 4
TST 4
V50.0
TST4
TST4
TST4
TST4
TST4
TST4
Bit 4
RES
RES
MODE
MODE
MODE
MODE
VCP.3
GRD0
GRD0
GRD0
V25.3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
Bit 3
RES
RES
VCP.2
EDG1
EDG1
EDG1
EDG1
SZEN
SZEN
SZEN
V25.2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
Bit 2
RES
RES
UPDT1
UPDT1
UPDT1
VCP.1
V25.1
EDG0
EDG0
EDG0
EDG0
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
Bit 1
RES
RES
UPDT0
UPDT0
UPDT0
SLOW
SLOW
SLOW
SLOW
VCP.0
V25.0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
Bit 0
LSb
RES
RES
Revision 0.4 (09-25-07)
Default
Value
CCh
CCh
CCh
CCh
4Dh
4Dh
0Ch
0Ch
0Ch
5Ah
N/A
N/A
N/A
09h
09h
N/A
00h
F1h
00h
N/A
Lock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
Start
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No