AD1837AAS Analog Devices Inc, AD1837AAS Datasheet - Page 12

• Manufacturer Part Number: AD1837AAS
• Description: IC CODEC 2ADC/8DAC 24BIT 52-MQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1837AAS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP
• For Use With: EVAL-AD1837AEB - BOARD EVALUATION FOR AD1837A

AD1837A
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal not be passed through an FPGA
or other large digital chip before being applied to the AD1837A.
In most cases, this will induce clock jitter due to the fact that
the clock signal is sharing common power and ground connec-
tions with other unrelated digital output signals.
Power-Down and RESET
PD/RST powers down the chip and sets the control registers to
their default settings. After PD/RST is de-asserted, an initialization
routine runs inside the AD1837A to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time, it is recommended that no SPI writes occur.
Power Supply and Voltage Reference
The AD1837A is designed for 5 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip capaci-
tors, as close to the pins as possible, to minimize noise pickup. A
bulk aluminum electrolytic capacitor of at least 22 mF should also
be provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate sup-
plies for the analog and digital sections. If this is not possible, it is
recommended that the analog and digital supplies be isolated by
MCLK
12.288MHz
CLATCH
CCLK
COUT
CIN
t
COE
t
CLS
D15
ADC OUTPUT
t
DAC INPUT
CLOCK SCALING
CCP
D14
2/3
1
2
48kHz/96kHz/192kHz
Figure 2. Modulator Clocking Scheme
48kHz/96kHz
t
COD
Figure 3. Format of SPI Timing
D9
D9
t
CCH
t
CDS
t
IMCLK = 24.576MHz
CCL
D8
D8
t
CDH
INTERPOLATION
–12–
OPTIONAL
FILTER
HPF
means of two ferrite beads in series with the bypass capacitor of
each supply. It is important that the analog supply be as clean
as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the V
Serial Control Port
The AD1837A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I
format, where the data is delayed by one BCLK interval from
the edge of the LRCLK. By changing Bits 6 to 8 in ADC
DECIMATOR/
DAC ENGINE
MODULATOR
ADC ENGINE
FILTER
S-D
REF
pin should be limited to less than 50 mA.
MODULATOR
DAC
S-D
D0
D0
t
CLH
t
COTS
ANALOG
OUTPUT
ANALOG
INPUT
REV. A
2
S