AD1980JSTZ Analog Devices Inc, AD1980JSTZ Datasheet - Page 24

• Manufacturer Part Number: AD1980JSTZ
• Description: IC CODEC STEREO 6-DAC 20B 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1980JSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1980
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the
BCA Bits in the EQ CNTRL register (60h). Data will only be written to memory if the EQM bit (Register 60h, Bit 15) is asserted.
CFD[15,0]
All register bits are read/write except for JS0ST and JS1ST, which are read only.
JS0INT
JS1INT
JS0ST
JS1ST
JS0MD
JS1MD
JS0TMR
JS1TMR
JS0EQB
JS1EQB
JSMT[2,0]
JS0DMX
JS1DMX
JSSPRD
Reg
No. Name
62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
Reg
No. Name
72h Jack
Sense
D15
JS1
SPRD DMX DMX MT2
D15
Coefficient Data. The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB and the CFD0 bit is the LSB.
Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR
should clear this bit by writing a “0” to it. Note that the interrupt to the system is actually an OR combination of
this bit and JS1INT. Also, note that the actual interrupt implementation is selected by the INTS bit (Register 76h).
It is also possible to generate a software system interrupt by writing a “1” to this bit.
Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR
should clear this bit by writing a “0” to it. See the JS0INT description for additional details.
JS0 STATE. This bit always reports the logic state of JS0 pin.
JS1 STATE. This bit always reports the logic state of JS1 pin.
JS0 Mode. This bit selects the operation mode for the JS0 pin.
0 = Jack Sense Mode (reset default)
1 = Interrupt Mode
JS1 Mode. This bit selects the operation mode for the JS1 pin.
0 = Jack Sense Mode (reset default)
1 = Interrupt Mode
JS0 Timer Enable. If this bit is set to a “1,” JS0 must be high for greater than 278 ms to be recognized.
JS1 Timer Enable. If this bit is set to a “1,” JS1 must be high for greater than 278 ms to be recognized.
JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to “1,” JS0 = 1 will
cause the EQ to be bypassed.
JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to “1,” JS1 = 1 will
cause the EQ to be bypassed.
JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table IX).
JS0 Down = Mix Control Enable. This bit enables JS0 to control the Down-Mix function. This function allows a
digital mix of six channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_out or
HP_out jacks. When this bit is set to “1,” JS0 = 1 will activate the Down-Mix conversion.
See the DMIX description in Register 76h. The DMIX bits select the Down-Mix implementation type and can also
force the function to be activated.
JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack
Senses are active (logic state “1”).
Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit’s
description in Register 76h for a better understanding of the Spread function.
JS Spread Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack Senses
are active (logic state “1”).
Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit’s
description in Register 76h for a better understanding of the Spread function.
D14
JS1
D14
D13
JS0
D13
D12
JS
D12
Jack Sense/Audio Interrupt Status Register (Index 72h)
JS
MT1
D11
D11
D10
JS
MT0
EQ Data Register (Index 62h)
D10
D9
JS1
EQB
D9
D8
JS0
EQB
–24–
D8
JS1
TMR
D7
D7
D6
JS0
TMR
D6
D5
JS1
MD
D5
D4
JS0
MD
D4
D3
D3
JS1
ST
D2
D2
JS0
ST
JS1
INT
D1
D1
JS0
INT
D0
D0
REV. 0
Default
Default
0000h