MCP2515-I/SO Microchip Technology, MCP2515-I/SO Datasheet - Page 39

• Manufacturer Part Number: MCP2515-I/SO
• Description: IC CAN CONTROLLER W/SPI 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2515-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 2.7V To 5.5V
• Driver Case Style: SOIC
• No. Of Pins: 18
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Supply Voltage Min: 2.7V
• Rohs Compliant: Yes
• Clock Frequency: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.2
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. Synchronization is
the
implemented.
When an edge in the transmitted data is detected, the
logic will compare the location of the edge to the
expected time (SyncSeg). The circuit will then adjust
the values of phase segment 1 and phase segment 2
as necessary.
There are two mechanisms used for synchronization:
1.
2.
5.2.1
Hard synchronization is only done when there is a
recessive-to-dominant edge during a BUS IDLE
condition, indicating the start of a message. After hard
synchronization, the bit time counters are restarted with
SyncSeg.
Hard synchronization forces the edge which has
occurred to lie within the synchronization segment of
the
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
5.2.2
As a result of resynchronization, phase segment 1 may
be lengthened or phase segment 2 may be shortened.
The amount of lengthening or shortening of the phase
buffer segments has an upper-bound given by the
Synchronization Jump Width (SJW).
The value of the SJW will be added to phase segment
1 or subtracted from phase segment 2 (see Figure 5-3).
The SJW represents the loop filtering of the DPLL. The
SJW is programmable between 1 T
5.2.2.1
The NRZ bit coding method does not encode a clock
into the message. Clocking information will only be
derived from recessive-to-dominant transitions. The
property that only a fixed maximum number of
successive bits have the same value (bit-stuffing)
ensures resynchronization to the bit stream during a
frame.
The phase error of an edge is given by the position of
the edge relative to SyncSeg, measured in T
phase error is defined in magnitude of T
• e = 0 if the edge lies within SYNCESEG.
• e > 0 if the edge lies before the SAMPLE POINT
• e < 0 if the edge lies after the SAMPLE POINT of
2003 Microchip Technology Inc.
(T
the previous bit (T
PhaseSeg2).
Q
Hard synchronization
Resynchronization
process
restarted
is added to PhaseSeg1).
Synchronization
HARD SYNCHRONIZATION
RESYNCHRONIZATION
Phase Errors
by
bit
Q
which
time. Due
is subtracted from
the
DPLL
to
Q
and 4 T
the
Q
as follows:
function
Q
rules
.
Q
. The
Preliminary
of
is
5.2.2.2
If the magnitude of the phase error is less than or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
5.2.2.3
If the magnitude of the phase error is larger than the
synchronization jump width and, if the phase error is
positive, phase segment 1 is lengthened by an amount
equal to the SJW.
5.2.2.4
If the magnitude of the phase error is larger than the
resynchronization jump width and the phase error is
negative, phase segment 2 is shortened by an amount
equal to the SJW.
5.2.3
1.
2.
3.
4.
5.
Only recessive-to-dominant edges will be used
for synchronization.
Only one synchronization within one bit time is
allowed.
An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
A transmitting node will not resynchronize on a
positive phase error (e > 0).
If the absolute magnitude of the phase error is
greater than the SJW, the appropriate phase
segment will adjust by an amount equal to the
SJW.
SYNCHRONIZATION RULES
No Phase Error (e = 0)
Positive Phase Error (e > 0)
Negative Phase Error (e < 0)
MCP2515
DS21801B-page 39