ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 4

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
3. Module: PHY (Transmit)
4. Module: Memory (SFR)
DS80477A-page 4
For 100Base-TX operation, the IEEE 802.3 speci-
fication requires the rise and fall times of the MLT3
signal to match within 0.5 ns, measured over
10 different intervals. The actual rise/fall time
symmetry measurements may occasionally be
slightly above this level.
This issue has no substantial impact on the quality
of the transmitted signal and will not impact
applications operating in real networks.
Work around
None.
Affected Silicon Revisions
The CRYPTEN bit (EIR<15>) cannot be
changed using the Bit Field Set (BFS), Bit Field
Clear (BFC), Bit Field Set Unbanked (BFSU) or
Bit Field Clear Unbanked (BFCU) SPI opcodes.
Similarly, when the PSP interface is being used,
CRYPTEN cannot be changed by writing to the
EIRSET or EIRCLR registers.
Work around
Set or clear the CRYPTEN bit using the Write
Control Register (WCR) or Write Control Regis-
ter Unbanked (WCRU) SPI opcodes, or a direct
PSP write to the EIR register.
If the application is not constrained by power
consumption, it is possible to set the CRYPTEN
bit at device initialization and leave it set.
If the application must change CRYPTEN at run
time, care must be taken to ensure that no
required interrupt flag bits in EIR are corrupted
in the process. For example, if the Link Change
Interrupt Flag, LINKIF (EIR<11>), is used by the
software, writing to EIR will cause potential loss
of information. This can be avoided by sampling
the interrupt source (PHYLNK bit in ESTAT)
before and after changing CRYPTEN. If the
PHYLNK bit has changed, the LINKIF bit can be
manually set through a safe BFS operation or
write to EIRSET. Any intermediate spurious
interrupts on the INT pin can be suppressed by
appropriately controlling the EIE interrupt
enable bits.
A2
X
5. Module: AES
Ideally, if using the SPI interface or using a PSP
interface with byte write capability, write only to
EIRH and avoid writing to EIRL.
Affected Silicon Revisions
At room temperature, the AES module may
compute valid results. However, across voltage,
temperature, and ordinary part-to-part device
variation, the AES engine will compute incorrect
results or fail to finish computations.
Work around
Use a software implementation of AES. For applica-
tions based on Microchip PIC
dsPIC
libraries documented in the Microchip Application
Notes AN953, “Data Encryption Routines for the
PIC18” or AN1044, “Data Encryption Routines for
PIC24 and dsPIC
these libraries is available on the Data Encryption
Libraries CD, Microchip part number SW300052.
Affected Silicon Revisions
A2
A2
X
X
®
digital signal controllers, consider using the
®
© 2009 Microchip Technology Inc.
Devices”. The source code for
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microcontrollers or