CS8900A-IQ3Z Cirrus Logic Inc, CS8900A-IQ3Z Datasheet - Page 127
![IC LAN ETHERNET CTLR 3V 100LQFP](/photos/6/81/68139/cs8900a-iq3z_sml.jpg)
CS8900A-IQ3Z
Manufacturer Part Number
CS8900A-IQ3Z
Description
IC LAN ETHERNET CTLR 3V 100LQFP
Manufacturer
Cirrus Logic Inc
Type
Single Chipr
Specifications of CS8900A-IQ3Z
Package / Case
100-LQFP
Controller Type
Ethernet Controller (IEEE 802.3)
Interface
ISA-BUS
Voltage - Supply
3V, 5V
Current - Supply
95mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Ethernet Connection Type
10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Supply Voltage (max)
6 V
Supply Voltage (min)
- 0.3 V
Supply Current (max)
+/- 10 mA
Maximum Operating Temperature
+ 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1163 - KIT EVAL FOR CS8900A
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1129
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
1 852
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
CIRRUS42
Quantity:
921
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS8900A-IQ3Z
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
CS8900A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS271F5
SWITCHING CHARACTERISTICS
CS8900A
Crystal LAN™ Ethernet Controller
DMA Read
DMACKx active to IOR active
AEN active to IOR active
IOR active to Data Valid
IOR inactive to SD 3-state
IOR n-1 high to DMARQx inactive
DMACKx, AEN hold after IOR high
16-Bit I/O Write
Address, AEN, SBHE valid to IOCS16 low
Address, AEN, SBHE valid to IOW low
IOW pulse width
SD hold after IOW high
IOW low to SD valid
IOW inactive to active
Address hold after IOW high
SA [15:0],
AEN, SBHE
IOCS16
IOW
SD [15:0]
DMARQx
DMACKx
SD[15:0]
Parameter
AEN
IOR
CIRRUS LOGIC PRODUCT DATASHEET
t
IOW2
t
DMA3
t
IOW1
Figure 53. 16-Bit DMA Read
Valid Address
Figure 54. 16-Bit I/O Write
t
IOW5
t
DMA2
t
DMA1
(Continued)
Valid
Data
t
IOW3
Valid Data In
t
DMA4
IOR
t
IOW7
n-1
Symbol
Valid
Data
t
t
t
t
t
t
DMAR1
DMAR2
DMAR3
DMAR4
DMAR5
DMAR6
t
t
t
t
t
t
t
t
IOW6
IOW1
IOW2
IOW3
IOW4
IOW5
IOW6
IOW7
t
IOW4
t
DMA5
t
DMA6
IOR
Min
110
60
10
20
20
35
n
Valid
Data
0
0
-
-
-
-
-
IN or OUT of chip
DIRECTION:
IN
OUT
IN
IN
IN or OUT of chip
DIRECTION:
Typ
30
-
-
-
-
-
-
-
-
-
-
-
OUT
IN
IN
IN
OUT
Max
135
20
35
10
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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