CY7C68320C-100AXC Cypress Semiconductor Corp, CY7C68320C-100AXC Datasheet
CY7C68320C-100AXC
Specifications of CY7C68320C-100AXC
CY7C68320C-100AXC
Available stocks
Related parts for CY7C68320C-100AXC
CY7C68320C-100AXC Summary of contents
Page 1
... QFN and 100-Pin TQFP Pb-free Packages ■ CY7C68321C is Ideal for Battery Powered Designs ■ CY7C68320C is Ideal for Self and Bus Powered Designs Features (CY7C68300C/CY7C68301C only) ■ Pin Compatible with CY7C68300A (using Backward Compatibility Mode) ■ 56-Pin SSOP and 56-Pin QFN Pb-free Packages ■ ...
Page 2
... EZ-USB AT2 (CY7C68300A). The USB CY7C68320C/321A (AT2LP) are connected to a host computer directly or with the downstream port of a USB hub. Software on the USB host system issues commands and sends data to the AT2LP and receives status and data from the AT2LP using standard USB protocol ...
Page 3
... AT2 to the AT2LP to help expedite the process. It can be downloaded from the Cypress website (http://www.cypress.com) or obtained through a Cypress representative. Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Figure 1. Simplified Pinout Selection Flowchart Read EEPROM EEPROM No Signature ...
Page 4
... Pin Diagrams The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C/301C is available in 56-pin SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs. ...
Page 5
... VCC DPLUS DMINUS GND VCC GND (PU10K) PWR500# GND Document 001-05809 Rev NOTE: Italic labels denote pin functionality during CY7C68300A compatibility mode. CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 42 RESET# 41 GND 40 ARESET# 39 DA2 (VBUS_PWR_VALID) 38 CS1# 37 CS0# 36 DRVPWRVLD (DA2) 35 DA1 34 DA0 33 INTRQ 32 VCC 31 DMACK# 30 DIOR# ...
Page 6
... Figure 4. 56-Pin SSOP Pinout (CY7C68320C/CY7C68321C) DD13 1 DD14 2 DD15 3 GND 4 GPIO2 5 VCC 6 GND 7 IORDY 8 DMARQ 9 AVCC 10 XTALOUT 11 XTALIN 12 AGND 13 VCC 14 DPLUS 15 DMINUS 16 GND 17 VCC 18 GND 19 GPIO1 20 GND 21 22 SCL SDA 23 VCC 24 DD0 25 DD1 26 DD2 27 DD3 28 Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C ...
Page 7
... Figure 5. 56-Pin QFN Pinout (CY7C68320C/CY7C68321C) IORDY 1 DMARQ 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 VCC 7 DPLUS 8 DMINUS 9 GND 10 VCC 11 GND 12 GPIO1 13 GND 14 Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 42 RESET# 41 GND 40 ARESET# 39 DA2 38 CS1# 37 CS0# 36 GPIO0 35 DA1 34 DA0 33 INTRQ 32 VCC 31 DMACK# 30 DIOR# 29 DIOW# Page ...
Page 8
... Figure 6. 100-Pin TQFP Pinout (CY7C68320C/CY7C68321C only) VCC 1 GND 2 IORDY 3 DMARQ 4 GND 5 GND 6 GND 7 GND 8 AVCC 9 XTALOUT 10 11 XTALIN AGND VCC 16 DPLUS 17 DMINUS 18 GND 19 VCC 20 GND 21 SYSIRQ 22 GND 23 24 GND GND 25 PWR500 GND NC 28 SCL 29 SDA 30 Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C ...
Page 9
... If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See 2. A ‘#’ sign after the pin name indicates that it is active LOW. 3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C. Document 001-05809 Rev. *B ...
Page 10
... NC 58 N/A N/A LOWPWR# 59 N/A N N/A N/A VBUSPWRD Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C (continued) Pin Default State Type at Startup No connect Active for Clock signal for I several ms at page 12). Apply a 2.2k pull up resistor. startup. 2 I/O Data signal for I C interface. (See page 12) ...
Page 11
... N/A GPIO0 [ GPIO1 [ GPIO2 91 GPIO3 92 GPIO4 93 GPIO5 Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C (continued) Pin Default State Type at Startup NC No connect. GND Ground. PWR V . Connect to 3.3V power source. CC [1] I Input ATA interrupt request. [1] O/Z Driven HIGH ATA address. after 2 ms ...
Page 12
... GND as shown in used, apply it to XTALIN and leave XTALOUT unconnected. Figure 7. XTALIN/XTALOUT Diagram Table 2 12pF Yes No Yes XTALIN CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C (continued) Pin Description on page 14). ± 100 ppm) signal to derive Figure alternate clock source is 24MHz Xtal 12pF XTALOUT Page [+] Feedback ...
Page 13
... Functions for Button Controls” details on HID functionality Figure 8. SYSIRQ Latching Algorithm No Yes Yes Yes CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C depicts the latching algorithm incorporated by on page 15 for more EP1 Data Byte SYSIRQ=1? Yes Latch State of IO Pins Set Int_Data = 1 No ...
Page 14
... VBUSPWRD State Pin VBUSPWRD = ‘1’ bMaxPower Reported Value bmAttributes bit 6 (bus-powered) Reported Value CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C on page 15 for more information on page 15 for more information VBUSPWRD = ‘0’ VBUSPWRD N/A (56-pin) 0xFA 0x01 The value (500 mA) (2 mA) from configu- ration address 0x34 is used ...
Page 15
... Command Document 001-05809 Rev. *B HID Functions for Button Controls Cypress’s CY7C68320C/CY7C68321C has the capability of through a CC supporting Human Interface Device (HID) signaling to the host. If there is a HID descriptor in the configuration data, the GPIO pins that are set as inputs are polled by the AT2LP logic approx- imately every 17 ms (depending on other internal interrupt routines) ...
Page 16
... Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Field Description This field indicates to the CY7C68300C/CY7C68301C that the ATACB contains a vendor-specific command block. This value of this field must match the value in EEPROM address 0x04 for the command to be recognized as a vendor-specific ATACB command. ...
Page 17
... Reserved Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Field Description This field controls which of the taskfile register read or write accesses occur. Taskfile read data is always 8 bytes in length, and unselected register data are returned as 0x00. Register accesses occur in sequential order as outlined here ...
Page 18
... Memory Data EZ-USB AT2LP (CY7C68300A) (AT2LP Pinout) Pinout Pinout No VBUS_ATA_ENABLE Pin HIGH? Yes No ARESET# Pin LOW? Yes DD7 Pin Set HIGH No ARESET# Pin HIGH? Yes Board Manufacturing Normal Mass Test Mode Storage Mode CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C “Fused Memory Page [+] Feedback ...
Page 19
... Reserved (0) 15–30 (0Fh1Eh) Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C EEPROM accesses (CfgCB) and one for board level testing (MfgCB), as described in the following sections. There is a convenient method available for starting the AT2LP in Board Manufacturing Test Mode to enable reprogramming of EEPROMs without a mass storage device attached ...
Page 20
... Mode operation. See Mfg_read data format. Any data length can be specified, but only bytes 0 through 3 contain usable information length of 4 bytes is recommended. Table 10. Mfg_read and Mfg_load Data Format Byte Bits 5:4 Bits 3 2 Table 10 for an expla 7:0 3 7:0 CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Bits ...
Page 21
... for EEPROM devices that are internally byte-addressed memories recommended that the address pins be set this way even on EEPROMs that may indicate that the address pins are internal no-connects. Figure 11. Snapshot of ‘AT2LP Blaster’ Utility CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C on page 19 for details on how Page [+] Feedback ...
Page 22
... IN packet before returning a STALL handshake for certain cases. Certain host controller drivers may require a short packet before STALL not force a short packet before STALL Force a short packet before STALL. CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x53 0x4B ...
Page 23
... PIO mode supported by the device. The AT2LP supports PIO modes 0, 3, and 4 only. PIO mode 0 is always enabled and has no corresponding configuration bit. Bit 1 = Enable PIO mode 4. Bit 0 = Enable PIO mode 3. CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0xD4 0x07 ...
Page 24
... AT2LP enumerates a removable ATA device, such as CompactFlash or MicroDrive, as the IDE master device. Enabling this pin also affects other pins related to removable device operation Disable removable ATA device support Enable removable ATA device support. CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x78 Page ...
Page 25
... ATA bus to discover the number of LUNs Search ATA bus and determine number of LUNs 01 = Assume only LUN0 present; no ATA bus search 10 = Assume LUN0 and LUN1 present; no ATA bus search 11 = Assume LUN0 and LUN1 present; no ATA bus search CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x00 ...
Page 26
... HID: 3 for CSM Length of device descriptor in bytes Type Descriptor type USB Specification release number in BCD USB Specification release number in BCD Device class Device subclass Device protocol CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x00 0x12 0x01 0x00 ...
Page 27
... Length of this descriptor in bytes Endpoint descriptor type This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size set by speed (Full speed 0x0040; High speed 0x0200) CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x40 0x01 0x00 ...
Page 28
... Interval for polling (max. NAK rate) Length of HID descriptor Descriptor Type HID HID Class Specification release number (1.10) Country Code Number of class descriptors (1 report descriptor) Descriptor Type Length of HID report descriptor CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x00 0x07 0x05 0x86 ...
Page 29
... Report Count 2 fields Output (Data, Variable, Absolute) End Collection Byte length of this descriptor Interface Descriptor type Number of interface Value used to select an alternate setting for the interface identified in prior field CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x06 0xA0 0xFF 0x09 ...
Page 30
... Method CSM Descriptor Version number LANGID string descriptor length in bytes Descriptor type Language supported. The CY7C68300B supports one LANGID value. String descriptor length in bytes (including bLength) Descriptor type CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x02 0x0D 0x00 0x00 0x00 ...
Page 31
... Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents ’C’ 0x43 0x00 ’y’ 0x79 0x00 ’p’ 0x70 0x00 ’ ...
Page 32
... Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x2C 0x03 ’U’ 0x55 0x00 ’S’ 0x53 0x00 ’ ...
Page 33
... ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character Amount of unused ROM space varies depending on strings. CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Required Variable Contents Contents 0x00 ’8’ 0x38 0x00 ’9’ 0x39 0x00 ’0’ 0x30 0x00 ’ ...
Page 34
... Data Source Starting Address Data Length 2 C memory device when none is connected result CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 2 C memory device Table 12. Attempts to write outside this 2 C memory device) remains unchanged. wLength Data Data Length ...
Page 35
... Unconfigured Current UNCONFIG T Reset Time After Valid Power RESET Pin Reset After Power Up Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Operating Conditions T (Ambient Temperature Under Bias) ............. 0°C to +70°C A Supply Voltage............................................+3.00V to +3.60V Ground Voltage.................................................................. 0V F (Oscillator or Crystal Frequency) .... 24 MHz ± 100 ppm, ...
Page 36
... SSOP Pb-free for self and bus powered designs CY7C68320C-56LTXC 56 QFN Sawn CY7C68321C-56LFXC 56 QFN Pb-free for battery-powered designs CY7C68321C-56LTXC 56 QFN Sawn CY7C68320C-100AXC 100 TQFP Pb-free for self and bus powered designs CY7C68321C-100AXC 100 TQFP Pb-free for battery-powered designs CY4615B EZ-USB AT2LP Reference Design Kit Note 4 ...
Page 37
... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS A CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 1.40±0.05 12°±1° SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. ...
Page 38
... Package Diagrams (continued) Figure 13. 56-Pin Shrunk Small Outline Package 056 Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 51-85062 *C Page [+] Feedback ...
Page 39
... Package Diagrams (continued) Document 001-05809 Rev. *B Figure 14. 56-Pin QFN LF56A Figure 15. 56-Pin QFN ( 0.9 MM) - Sawn CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C 51-85144 *G Page 001-53450 ** [+] Feedback ...
Page 40
... Via hole for thermally connecting the QFN to the circuit board ground plane. Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB ...
Page 41
... Designs that utilize separate power supplies for the CY7C68300C/CY7C68301C and the ATA/ATAPI device are not recommended. Document 001-05809 Rev. *B CY7C68300C, CY7C68301C CY7C68320C, CY7C68321C Figure 18 displays an X-Ray image of assembly (darker areas indicate solder). Figure 18. X-Ray Image of the Assembly IDE Removable Media Devices The AT2LP does not fully support IDE removable media devices ...
Page 42
... Change GIR New data sheet. ARI/KKU Implemented new template. Added part number CY7C68320C-56PVXC to the Ordering Information. Corrected part numbers on figure 5 and 6. Moved figure titles to the top of each figure per new template requirements. Made grammatical corrections. Changed the Fused Memory Data section. Added new figure: 56-pin SSOP (CY7C68320C/CY7C68321C) ...