Z8523020VSG Zilog, Z8523020VSG Datasheet - Page 75

• Manufacturer Part Number: Z8523020VSG
• Description: IC 20MHZ ESCC 44-PLCC
• Manufacturer: Zilog

Specifications of Z8523020VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 9mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3928; Z8523020VSG

Z80230 Interface Timing
PS005303-0907
Z80230 Write Cycle Timing
The Z-Bus compatible ESCC is suited for system applications with multiplexed address/
data buses.
Two control signals, AS and DS, are used by the Z80230 to control bus transactions. Addi-
tionally, four other control signals (CS0, CS1, RW, and INTACK) control the type of bus
transaction that occurs. A bus transaction is initiated by AS. The rising edge latches the
register address on the Address/Data bus and the state of INTACK and CS0.
In addition to bus transactions, the interrupt section uses the AS to set Interrupt Pending
(IP) bits. Therefore, AS must be kept cycling for the interrupt section to function.
The Z80230 generates internal control signals in response to a register access. Because AS
and DS have no defined phase relationship with PCLK, the circuitry generating these
internal control signals provide time for metastable conditions to disappear. This action
results in a recovery time related to PCLK.
This recovery time applies only to transactions involving the Z80230, and any intervening
transactions are ignored. This recovery time is four PCLK cycles, measured from the fall-
ing edge of DS for one access to the ESCC, to the falling edge of DS for a subsequent
access.
INTACK
A7–A0
CS0
R/W
CS1
DS
AS
Figure 17
Figure 17. Z80230 Write Cycle Timing
illustrates the Write cycle timing.
Address
Data Valid
Product Specification
Z80230 Interface Timing
Z85230/Z80230
70