USBN9604-28M/NOPB National Semiconductor, USBN9604-28M/NOPB Datasheet - Page 29

• Manufacturer Part Number: USBN9604-28M/NOPB
• Description: IC CONTROLLER SERIAL BUS 28-SOIC
• Manufacturer: National Semiconductor

Specifications of USBN9604-28M/NOPB

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: USBN9604-HS-EB - KIT NODE CONTROLLER SAMPLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *USBN9604-28M; *USBN9604-28M/NOPB; USBN9604-28M

6.0 Functional Description
The device exits Halt mode in response to one of the following wake-up events:
When a valid wake-up event is detected, the device returns to active mode after a power-up delay of 2
has elapsed (approximately 680 usec ). This delay is established by a 14-bit delay counter, which ensures that the 24 MHz
oscillator has reached a stable condition and the clock doubler locks and generates a stable 48 MHz signal. After this start-
up delay, the clock signal can be output on the CLKOUT pin.
6.4 CLOCK GENERATION
The Clock Generator provides the CLKOUT output signal based on the programming of the Clock Configuration register
(CCONF). This allows disabling of the output clock and selection of a clock divisor. The clock divisor supports a program-
mable output in the range of 48 MHz to 2.82 MHz. On a power-on reset, the output clock defaults to 4 MHz. A software reset
has no effect on the programming of the CCONF, and thus no effect on the CLKOUT signal.
The only difference between the USBN9603 and USBN9604 devices is the effect of a hardware reset on the clock gener-
ation circuit. In the USBN9604, assertion of the RESET input causes the clock generation circuit to be reset, whereas in the
USBN9603, the clock generation circuit is not reset.
In the USBN9603, however, assertion of the RESET input does cause all registers to revert to their reset values, including
CCONF, which then forces the CLKOUT signal to its default of 4 MHz.
In the USBN9604, assertion of the RESET input causes the clock generation circuit to be reset as with the power-on reset.
As part of the clock generation reset, a delay of 2
sertion of the RESET input also causes all registers to revert to their reset values, including CCONF, which then forces the
CLKOUT signal to its default of 4 MHz.
This difference is particularly important for bus-powered operations. In such applications, the voltage provided by the bus
may fall below acceptable levels for the clock generation circuit. When this occurs, a reset must be applied to this circuit to
guarantee proper operation. After a delay of 2
is typically accomplished in bus-powered applications using a voltage sensor, such as the LP3470, to appropriately reset
the CPU and other components, including the USBN9604.
In self-powered applications where there is direct control over the voltage supply, there is no need for the RESET input to
cause the clock generation circuitry to be reset and the CLKOUT signal to stall for 2
thus suited for self-powered applications that use the CLKOUT signal as a system clock.
A high-to-low transition is detected on the CS pin and the wake-up Enable bit, ENUC in the WKUP register, is set to
1.
Any activity on the USB is detected (USB not idle) and the wake-up Enable bit, ENUSB in the WKUP register is set
to 1. (The node can detect any USB activity only when it is attached.)
Power-On Reset
External RESET
Wake-Up
Event
Halt
(Continued)
Figure 24. Power Saving Modes
14
XIN clock cycles, the CLKOUT signal is output. This low voltage detection
14
Halt On Suspend
or Force Halt
XIN clock cycles is incurred before the CLKOUT signal is output. As-
Power-Up
Delay
29
2
14
Power-Up Delay
Timeout
cycles
Active
14
XIN clock cycles. The USBN9603 is
14
XIN clock cycles
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