USB3300-EZK SMSC, USB3300-EZK Datasheet - Page 20
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USB3300-EZK
Manufacturer Part Number
USB3300-EZK
Description
IC USB HOST/OTG PHY ULPI 32-QFN
Manufacturer
SMSC
Type
Hi Speed USB Host Devicer
Datasheet
1.USB3300-EZK.pdf
(55 pages)
Specifications of USB3300-EZK
Controller Type
USB 2.0 Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-QFN
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1034
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
USB3300-EZK
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
USB3300-EZK-TR
Manufacturer:
MICRON
Quantity:
3 140
Part Number:
USB3300-EZK-TR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Revision 1.08 (11-07-07)
6.1.1
STP
POR
Overview
Figure 6.2
does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.
The advantage of a “wrapper less” architecture is that the PHY has a lower USB latency than a design
which must first register signals into the PHY’s wrapper before the transfer to the PHY core. A low
latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-
around timing given in the USB 2.0 specification.
RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3300
uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This
low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This
is the result of the “wrapper less” architecture of the USB3300. This low RxEndDelay should allow
legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface.
Data[7:0]
NXT
DIR
illustrates the block diagram of the ULPI digital functions. It should be noted that this PHY
ULPI Register
ULPI Protocol
Block
Array
Rx Data
Figure 6.2 ULPI Digital Block Diagram
Tx Data
InterruptEnable Rise[4:0]
InterruptEnableFall[4:0]
XcvrSelect[1:0]
TermSelect
OpMode[1:0]
Reset
SuspendM
6pinSerial Mode
3pinSerial Mode
ClockSuspendM
AutoResume
Interface Protect Disable
Indicator Complement
Indicator Pass Thru
IdPullUp
DpPulldown
DmPulldown
DischrgVbus
ChrgVbus
DrvVbus
DrvVbusExternal
UseExternal Vbus Indicator
DATASHEET
InterruptStatus[4:0]
InterruptLatch[4:0]
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
RXD CMD
20
High Speed Data
Full / Low Speed
High Speed TX
Low Speed TX
Full Speed TX
Data Recovery
Recovery
Transceiver
Interrupt
Control
Control
Module
To USB
Transceiver
To OTG
Module
HS Tx Data
FS/LS Tx Data
HostDisconnect
NOTE:
The USB3300 uses
a wrapperless ULPI
interface.
Linestates[1:0]
HS RX Data
SessionValid
FS/LS Data
SessionEnd
VbusValid
IdGnd
To USB
Transceiver
From OTG
Module
From USB
Transceiver
SMSC USB3300
Datasheet