LAN9500-ABZJ SMSC, LAN9500-ABZJ Datasheet - Page 5

• Manufacturer Part Number: LAN9500-ABZJ
• Description: IC USB 2.0 ETHER CTRLR 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9500-ABZJ

• Controller Type: USB 2.0 Controller
• Interface: MII
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 78mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 97.5 mA, 135.2 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10BASE-T or 100BASE-TX
• Maximum Power Dissipation: 0.6657 W (Typ)
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1071

Hi-Speed USB 2.0 to 10/100 Ethernet Controller
LAN9500/LAN9500i Product Introduction
Chapter 1 Introduction
SMSC LAN9500/LAN9500i
1.1
1.2
JTAG
USB
LAN9500/LAN9500i
Overview
Block Diagram
The LAN9500/LAN9500i is a high performance, small form factor solution for USB to 10/100 Ethernet
port bridging. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB
port replicators, USB to Ethernet adapters, PC docking stations, and test instrumentation, the
LAN9500/LAN9500i is targeted as a high performance, low cost USB/Ethernet connectivity solution.
The LAN9500/LAN9500i contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0
device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with
a total of 30 KB of internal packet buffering. The internal Ethernet PHY may be optionally disabled.
When not using the internal Ethernet PHY, an external MII interface is available for an external Fast
Ethernet PHY, HomePNA, or HomePlug functionality.
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed
standard. The LAN9500/LAN9500i implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is
compliant with the IEEE 802.3 and IEEE 802.3u standards.
An internal EEPROM controller exists to load various USB configuration information and the device
MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
Additionally, host management is available via USB in-band vendor commands (Register Read /
Register Write).
Multiple power management features are provided, including various low power modes and "Magic
Packet", "Wake On LAN", and "Link Status Change" wake events. These wake events can be
programmed to initiate a USB remote wakeup.
LAN9500/LAN9500i software drivers are available for Windows XP, Windows Vista, Mac OSX, Linux,
and Win CE. In addition, manufacturing and diagnostic tools are available for debugging and external
EEPROM configuration.
Controller
USB
PHY
TAP
Controller
USB 2.0
Device
Figure 1.1 LAN9500/LAN9500i Block Diagram
PRODUCT INTRODUCTION
Controller
SRAM
FIFO
(30KB)
5
Ethernet
10/100
MAC
Controller
EEPROM
Ethernet
PHY
Revision 1.1 (06-25-08)
MII: To optional
external PHY
Ethernet
EEPROM