LAN9500-ABZJ SMSC, LAN9500-ABZJ Datasheet - Page 13

• Manufacturer Part Number: LAN9500-ABZJ
• Description: IC USB 2.0 ETHER CTRLR 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9500-ABZJ

• Controller Type: USB 2.0 Controller
• Interface: MII
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 78mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 97.5 mA, 135.2 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10BASE-T or 100BASE-TX
• Maximum Power Dissipation: 0.6657 W (Typ)
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1071

USB 2.0 to 10/100 Ethernet Controller
Datasheet
SMSC LAN950x Family
NUM PINS
1
1
1
1
1
1
1
Carrier Sense
Purpose I/O 3
Purpose I/O 0
Purpose I/O 1
Receive Error
Receive Data
(Internal PHY
(Internal PHY
(Internal PHY
Management
MII Collision
PHY Mode)
PHY Mode)
PHY Mode)
PHY Mode)
PHY Mode)
Mode Only)
PHY Mode)
Mode Only)
PHY Mode)
Mode Only)
(External
(External
(External
(External
(External
(External
(External
Transmit
Receive
General
General
General
Enable
NAME
Detect
Clock
Valid
Data
SYMBOL
RXCLK
GPIO3
GPIO0
GPIO1
RXER
RXDV
TXEN
MDIO
CRS
COL
Table 3.1 MII Interface Pins
DATASHEET
BUFFER
IS/O8/
IS/O8/
IS/O8/
TYPE
IS/O8
(PD)
(PD)
(PD)
(PD)
(PD)
OD8
(PU)
(PD)
OD8
(PU)
(PD)
OD8
(PU)
O8
IS
IS
IS
IS
IS
13
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
receive error in the packet. In internal PHY mode,
this pin is not used.
In external PHY mode, this pin functions as an
output to the external PHY and indicates valid
data on TXD[3:0]. In internal PHY mode, this pin
is not used.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates valid
data on RXD[3:0]. In internal PHY mode, this pin
is not used.
In external PHY mode, this pin is the receiver
clock input from the external PHY. In internal
PHY mode, this pin is not used.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
network carrier.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
collision event.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
In external PHY mode, this pin provides the
management data to/from the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
(LAN9500A/LAN9500Ai only)
This pin may be used to signal PME
when Internal PHY and PME modes of
operation are in effect. Refer to
Chapter 6, "PME Operation," on
page 40
(LAN9500A/LAN9500Ai only)
This pin may serve as the
PME_MODE_SEL input when Internal
PHY and PME modes of operation are
in effect. Refer to
Operation," on page 40
information.
DESCRIPTION
for additional information.
Chapter 6, "PME
Revision 1.0 (05-17-10)
for additional