AT83C26-ZTUL Atmel, AT83C26-ZTUL Datasheet - Page 25

• Manufacturer Part Number: AT83C26-ZTUL
• Description: IC SMART CARD READER 1/PM 48-QFN
• Manufacturer: Atmel

Specifications of AT83C26-ZTUL

• Controller Type: Smart Card Reader Interface
• Interface: 2-Wire
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• For Use With: AT89STK-09 - EVAL BOARD FOR AT83C26
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Software activation for SCn (n=1, 2, 3, 4, 5) interfaces and ARTn bit = 1
Automatic Reset Transition description:
7511D–SCR–02/07
Note:
The following sequence can be applied:
A 16-bit counter starts when CARDRSTn bit is set. It counts card clock cycles. The CRSTn sig-
nal is set when the counter reaches the TIMER_MSB and TIMER_LSB value which corresponds
to the “tb” time (Figure 15).The counter is reseted when the CRSTn pin is released and it is
stopped at the first start bit of the Answer To Request (ATR) on CIOn pin.
The CIOn pin is not checked during the first 200 clock cycles (ta, Figure 15). If the ATR arrives
before the counter reaches TIMER_MSB and TIMER_LSB values, the activation sequence fails,
Figure 14. Software activation without automatic control (ARTn bit = 0)
–
–
1. Card Voltage is set by software to the required value (VCARDn1:0] bits in
2. Wait of the end of the DC/DC init (or LDO) with a polling on VCARD_OKn bit or wait
3. CKSTOPn, IODISn are programmed by software. CKSTOPn bit is reset to have the
4. CARDRSTn bit is set by software.
It is assumed that initially VCARDn[1:0], CARDCKn, CARDIOn and CARDRSTn bits
are cleared, CKSTOPn and IODISn are set (those bits are further explained in the
registers description)
The user should check the AT83C26 status and possibly resume the activation
sequence if one TWI transfer is not acknowledged during the activation sequence.
SCn_CFG0 register). This writing starts the DC/DC converter (or LDO).
for INT to go Low. When VCARD_OKn bit is set (by hardware), CARDIOn bit should
be set by software.
clock running. IODISn is reset to enable the transparent mode on CIOn,CC4n,
CC8n.
CVCCn
CRSTn
CCLKn
CIOn
1
2
3
4
ATR
AT83C26
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