AT83C26-ALRUL Atmel, AT83C26-ALRUL Datasheet - Page 47

• Manufacturer Part Number: AT83C26-ALRUL
• Description: IC SMART CARD READER 1/PM 48VQFP
• Manufacturer: Atmel

Specifications of AT83C26-ALRUL

• Controller Type: Smart Card Reader Interface
• Interface: 2-Wire
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: AT89STK-09 - EVAL BOARD FOR AT83C26
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 26. SC2_CFG2 ()
7511D–SCR–02/07
Bit Number
ART2
2-0
7
7
6
5
4
3
CRST_SEL2
Bit Mnemonic
CRST_SEL2
CARDRST2
CARDCK2
CKSTOP2
CKS2[2:0]
6
ART2
Reset value = 0x00001000
Notes:
CARDRST2
1. When CKS2 value is changed a special logic insures no glitch occurs on the CCLK2 pin and
2. CCLK2 must be stopped with CKSTOP2 bit before switching from CKS2 = (0, 1, 2, 3, 6, 7) to
Description
Automatic Reset Transition
Set this bit to have the CRST2 pin changed according to activation sequence.
Clear this bit to have the CRST2 pin immediately following the value programmed in CARDRST2.
Card Reset Selection
Set this bit to have the CRST2 pin driven by hardware through the A1/RST pin.
Clear this bit to have the CRST pin driven by software through the CARDRST bit.
The reset value is 0.
Card Reset
Set this bit to enter a reset sequence according to ART2 bit value.
Clear this bit to drive a low level on the CRST2 pin.
Card Clock
Set this bit to set a high level on the CCLK2 pin (according to CKSTOP2 bit value).
Clear this bit to drive a low level on the CCLK2 pin.
CARD Clock Stop
Set this bit to stop CCLK2 according to CARDCK2. This can be used to set asynchronous cards in power-
down mode (GSM) or to drive CCLK2 by software.
Clear this bit to have CCLK2 running according to CKS2. This can be used to activate asynchronous cards.
Note:
Interface 2 Card Clock Selection
CKS2 [2:0] = 0: CCLK2 = CLK (then the maximum frequency is 24 MHz)
CKS2 [3:0] = 1: CCLK2 = DCCLK
CKS2 [3:0] = 2: CCLK2 = DCCLK / 2
CKS2 [3:0] = 3: CCLK2 = DCCLK / 4
CKS2 [3:0] = 4: CCLK2 = A2
CKS2 [3:0] = 5: CCLK2 = A2 / 2
CKS2 [3:0] = 6: CCLK2 = CLK / 2
CKS2 [3:0] = 7: CCLK2 = CLK / 4
actual configuration changes can be delayed by half a period to two periods of CCLK2.
CKS2 = (4, 5) or vice versa.
5
When this bit is changed a special logic ensures that no glitch occurs on the CCLK2 pin and actual
configuration changes can be delayed by half a period to two periods of CCLK2.
CARDCK2
4
CKSTOP2
3
CKS22
2
CKS21
1
AT83C26
CKS20
0
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