ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 11

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
9397 750 13959
Product data
7.5 GoodLink
7.6 Bit clock recovery
7.7 Voltage regulator
7.8 PLL clock multiplier
7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface
V
Without V
With V
there is noise on the (D+, D-) lines, it is not taken into account. This ensures that the
peripheral remains in the suspend state.
Remark: Note that the tolerance of the internal resistors is 25 %. This is higher than
the 5 % tolerance specified by the USB specification. However, the overall voltage
specification for the connection can still be met with a good margin. The decision to
make use of this feature lies with the USB equipment designer.
Indication of a good USB connection is provided at pin GL through GoodLink
technology. During enumeration, the LED indicator will blink on momentarily. When
the ISP1181A has been successfully enumerated (the peripheral address is set), the
LED indicator will remain permanently on. Upon each successful packet transfer (with
ACK) to and from the ISP1181A, the LED will blink off for 100 ms. During ‘suspend’
state, the LED will remain off.
This feature provides a user-friendly indication of the status of the USB peripheral,
the connected hub, and the USB traffic. It is a useful field diagnostics tool for isolating
faulty equipment. It can therefore help to reduce field support and hotline overhead.
The bit clock recovery circuit recovers the clock from the incoming USB data stream
using a 4 times over-sampling principle. It is able to track jitter and frequency drift as
specified by the USB Specification Rev. 2.0 .
A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver
and internal logic. This voltage is available at pin V
pull-up resistor on the D line. Alternatively, the ISP1181A provides SoftConnect
technology via an integrated 1.5 k pull-up resistor (see
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1181A appears as a
memory device with an 8/16-bit data bus and a 1-bit address line. The ISP1181A
supports both multiplexed and non-multiplexed address and data buses.
The ISP1181A can also be configured as a DMA slave device to allow more efficient
data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the
local shared memory. The DMA interface can be configured independently from the
PIO interface.
BUS
sensing prevents the peripheral from wake-up when V
BUS
BUS
sensing, (D+, D-) is decoupled when no V
sensing, any activity or noise on (D+, D-) might wake up the peripheral.
Rev. 05 — 08 December 2004
Full-speed USB peripheral controller
reg(3.3)
BUS
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
is present. Therefore, even if
to supply an external 1.5 k
Section
BUS
is not present.
ISP1181A
7.4).
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