KSZ8873MLL AM Micrel Inc, KSZ8873MLL AM Datasheet - Page 12

• Manufacturer Part Number: KSZ8873MLL AM
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873MLL AM

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant
• Other names: 576-3633; KSZ8873MLL AM; KSZ8873MLLAM

Micrel, Inc.
September 2009
Pin Number
28
29
30
31
32
33
34
35
36
37
38
39
40
SMRXD32
SMRXD31
SCRS3/
SCOL3/
SMRXC3/
VDDC
SPIQ
SPISN
Pin Name
SMRXDV3
SMRXD33/
REFCLKO_3
GND
SMRXD30
NC
NC
NC
GND
Type
lpu/O
lpu/O
Ipu/O
Ipu/O
Gnd
lpu/O
I/O
I/O
I/O
Gnd
lpu/O
P
I
(1)
Description
Switch MII receive data valid
Strap option: MII mode selection
PU = PHY mode.
PD = MAC mode
MLL/FLL: Switch MII receive data bit 3/
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = enable
PD = disable
Switch MII receive data bit 2
Strap option: Force the speed on port 2 (P2SPD)
Switch MII receive data bit 1
Strap option: Force duplex mode (P2DPX)
negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0.
auto-negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0.
Digital ground
Switch MII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
negotiation result.
MLL/FLL: Switch MII carrier sense
RLL: No connection, Internal pull up.
MLL/FLL: Switch MII collision detect
RLL: No connection, Internal pull up.
MLL/FLL: Switch MII receive clock.
RLL: No Connection.
Digital ground
Ferrite bead and capacitor.
SPI slave mode: serial data output
Note: an external pull-up is needed on this pin when it is in use.
Strap option: XCLK Frequency Selection
PU = 25 MHz
PD = 50 MHz
When SPISN is high, the KSZ8873MLL/FLL/RLL is deselected and SPIQ
is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note: an external pull-up is needed on this pin when it is in use.
1.8 digital VDD input power supply from VDDCO (pin 58) through external
SPI slave mode: chip select (active low)
PD = force port 2 to 10BT if P2ANEN = 0
PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-
PU = always enable (force) port 2 flow control feature.
PU = force port 2 to 100BT if P2ANEN = 0
PD (default) = Port 2 default to half duplex mode if P2ANEN = 1 and
PD = port 2 flow control feature enable is determined by auto-
Output in PHY MII mode
Input in MAC MII mode
12
KSZ8873MLL/FLL/RLL
M9999-092309-1.2