KSZ8873MLL AM Micrel Inc, KSZ8873MLL AM Datasheet - Page 34
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KSZ8873MLL AM
Manufacturer Part Number
KSZ8873MLL AM
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL AM
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant
Other names
576-3633
KSZ8873MLL AM
KSZ8873MLLAM
KSZ8873MLL AM
KSZ8873MLLAM
Micrel, Inc.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive
enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following table
shows the port setting and software actions taken for each of the five spanning tree states.
September 2010
Disable State
The port should
not forward or
receive any
packets. Learning
is disabled.
Blocking State
Only packets to
the processor are
forwarded.
Learning is
disabled.
Listening State
Only packets to
and from the
processor are
forwarded.
Learning is
disabled.
Learning State
Only packets to
and from the
processor are
forwarded.
Learning is
enabled.
Forwarding
State
Packets are
forwarded and
received normally.
Learning is
enabled.
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
Port Setting
“transmit
enable = 0,
receive
enable = 0,
learning
disable = 0”
Port Setting
“transmit
enable = 1,
receive
enable = 1,
learning
disable = 0”
Software Action
The processor should not send any packets to the port. The switch may still
send specific packets to the processor (packets that match some entries in
the “static MAC table” with “overriding bit” set) and the processor should
discard those packets. Address learning is disabled on the port in this
state.
Software Action
The processor should not send any packets to the port(s) in this state. The
processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
also be set so that the switch will forward those specific packets to the
processor. Address learning is disabled on the port in this state.
Software Action
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state. See
“Tail Tagging Mode” for details. Address learning is disabled on the port in
this state.
Software Action
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state. See
“Tail Tagging Mode” for details. Address learning is enabled on the port in
this state.
Software Action
The processor programs the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit is set so
that the switch forwards those specific packets to the processor. The
processor can send packets to the port(s) in this state. See “Tail Tagging
Mode” for details. Address learning is enabled on the port in this state.
Table 12. Spanning Tree States
34
KSZ8873MLL/FLL/RLL
M9999-092309-1.2