Z87L0116FSC1937 Zilog, Z87L0116FSC1937 Datasheet - Page 22

• Manufacturer Part Number: Z87L0116FSC1937
• Description: IC FHSS CORDLESS TEL CTRL 144QFP
• Manufacturer: Zilog

Specifications of Z87L0116FSC1937

• Controller Type: Phone Controller
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 55mA
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Transmit 4-Bit DAC
The transmit DAC clocks one new NCO value out of the
Z87001 every 8.192 MHz period. Only the 10.7 MHz alias
frequency component of the transmit signal (2.508 + 8.192
MHz image) is filtered, amplified and upconverted to the
900 MHz ISM band by the companion RF module.
Event Trigger Block
The event trigger block is responsible for scheduling the
different events happening at the bit and frame levels. The
event trigger block receives input from the frame counters
as well as the register interface of the DSP core processor.
The event trigger schedules the following events:
4-Bit DAC for Setting Transmit Power Level
In order to save battery life, the Z87001 only transmits the
amount of RF power needed to reach the remote receiver
with a sufficient SNR margin. The on-board transmit power
4-bit DAC provides 4 different voltage levels to the power
amplifier in the RF module for that purpose. This DAC is di-
22
Start of the 4 ms frame: a synthesizer load enable pulse
is issued on the SYLE pin
Power-up of the modulator section and transmission of
the frame on handset and base station
Use of the bit inversion as function of mode
Power-up of the demodulator section and reception of
the frame on handset and base station
Control of PAON and TXSW output pins, to be used as
TDD control signals for the T/R switch as well as the
transmitter and receiver chains on the RF module
Control of RFEON pin, to be used as general on/off
switch on the RF module
Control of the Z87001 sleep mode
Tx signal
4-bit DAC
Figure 3. Modulator Block Diagram
P R E L I M I N A R Y
NCO
rectly controlled by the Z87001 software through an output
register.
8-Bit ADC for Sampling the Received Signal
Strength Indicator (RSSI)
RSSI information is typically generated from the last stage
of the RF receiver. The RSSI is sampled once per frame
by the 8-bit ADC and used by the Z87001 software to com-
pute the necessary Transmit Power Level voltages.
DSP Core Processor
A DSP core processor constitutes the heart of the Z87001.
The DSP runs the application software which performs the
following functions:
Register initialization
Implementation of high-level phone features; control of
phone user interface (keypad, Led, etc.)
Control of the Z87010 ADPCM Processor
Control of the phone line interface
Ring detection by DSP processing
Communication protocol between handset and base
station supporting voice and signalling channels
Control of the RF synthesizer and adaptive frequency
hopping algorithm
Control of the RF power and adaptive power algorithm
Control of the demodulator (bit synchronizer loop filter,
AFC bias estimate filtering)
Control of the modulator (carrier frequency) and
adaptive frequency alignment
Signalling between base and handset to support above
features
Spectral
Shaping
Tx Buffer
DS96WRL0800
Zilog