IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 112
IDT82V2108PXG8
Manufacturer Part Number
IDT82V2108PXG8
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PXG8
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V2108PXG8
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2108PXG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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IDT82V2108
OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H)
should be set to logic 0. The THDLC Lower Transmit Threshold should
be set to such a value that sufficient warning of an underrun is given.
The procedure shown in Figure 76 should be followed.
Operation
Figure 76. Polling Mode in E1 Mode HDLC Transmitter
- Polling Mode
In the packet transmission polling mode, the FULLE (b3, E1-053H),
Y
into the THDLC FIFO
Write the data
be tarnsmitted
More Data to
interrupt status
Read THDLC
THDLC initial
available
FULL=1
Data is
Set EOM
N
N
Y
N
Y
Wait, until FULL=0
or BBLFILL=1
102
example is shown in Table 44.
Table 44: Example for Using HDLC Transmitter
Register
00AH
02AH
02BH
050H
050H
053H
055H
055H
055H
055H
055H
055H
055H
055H
050H
To summarize the procedure of using HDLC Transmit, a complete
Value
C4H
C3H
BCH
DEH
58H
FFH
83H
0FH
12H
34H
56H
78H
9AH
FFH
8BH
THDLC #2 is selected. The HDLC Transmit is accessi-
ble to the CPU interface.
TS4 of even frames and odd frames is selected.
All the 8 bits are selected.
The function of the THDLC #2 is enabled. The FCS is
enabled and the THDLC FIFO is reset.
Enable the THDLC Interrupt Enable bits.
Write data into THDLC FIFO.
End of packet and set the EOM to ‘1’.
T1 / E1 / J1 OCTAL FRAMER
Description
March 5, 2009
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