DS3141+ Maxim Integrated Products, DS3141+ Datasheet - Page 65
DS3141+
Manufacturer Part Number
DS3141+
Description
IC FRAMER DS3/E3 SNGL 144CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3141.pdf
(88 pages)
Specifications of DS3141+
Controller Type
DS3/E3 Framer
Interface
LIU
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
80mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE). This bit enables an interrupt if the TFIL bit in the
register is set.
Bit 1: Receive FEAC Codeword Detected Interrupt Enable (RFCDIE). This bit enables an interrupt if the RFCDL
Bit 2: Receive FEAC Idle Interrupt Enable (RFIIE). This bit enables an interrupt if the RFIL bit in the
register is set.
Bit 3: Receive FEAC FIFO Not-Empty Interrupt Enable (RFFNIE). This bit enables an interrupt if the RFFNL bit
in the
Bit 4: Receive FEAC FIFO Overflow Interrupt Enable (RFFOIE). This bit enables an interrupt if the RFFOL bit in
the
Figure 7-8. FEAC Status Bit Interrupt Signal Flow
FSRL
RECEIVE FIFO
TRANSMIT FEAC
RECEIVE FIFO
FSRL
RECEIVER IN
OVERFLOW
DETECTED
IDLE STATE
CODEWORD
0 = interrupt disabled
1 = interrupt enabled
bit in the
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
IDLE STATE
DETECTED
RECEIVE
register is set.
EMPTY
register is set.
N/A
—
FSRL
7
register is set.
POS EDGE
NEG EDGE
POS EDGE
DETECT
DETECT
DETECT
POS EDGE
POS EDGE
DETECT
DETECT
N/A
—
6
FRSIE.RFFOIE
FSRIE.RFFNIE
FSRIE
FEAC Status Register Interrupt Enable
63h
LATCH
LATCH
LATCH
FSRIE.RFIIE
LATCH
LATCH
FSRIE.RFCDIE
FSRIE.TFIIE
N/A
—
5
FSR.RFI
FSRL.RFIL
FSR.RFFE
FSRL.RFFNL
FSRL.RFFOL
FSR.TFI
FSRL.TFIL
FSR.RFCD
FSRL.RFCDL
RFFOIE
65 of 88
0
4
RFFNIE
3
0
MSR.FEAC
MSRIE.FEACIE
RFIIE
2
0
RFCDIE
1
0
INT PIN (ORed
WITH OTHER
SOURCES)
TFIIE
0
0
FSRL
FSRL
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