DS2143Q/T&R Maxim Integrated Products, DS2143Q/T&R Datasheet - Page 26

IC CONTROLLER E1 5V LP 44-PLCC

DS2143Q/T&R

Manufacturer Part Number
DS2143Q/T&R
Description
IC CONTROLLER E1 5V LP 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2143Q/T&R

Controller Type
E1 Controller
Interface
Parallel/Serial
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2143Q/T&RDS2143Q/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represents a timeslot in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first.
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins
respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either
high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
13 for an example.
(MSB)
(MSB)
CH16
CH24
CH32
TIDR7
CH8
SYMBOL
SYMBOL
TIDR7
TIDR0
CH32
CH1
CH15
CH23
CH31
CH7
TIDR6
POSITION
POSITION
CH14
CH22
CH30
CH6
TIDR.7
TIDR.0
TIR4.7
TIR1.0
TIDR5
CH13
CH21
CH29
CH5
NAME AND DESCRIPTION
Transmit Idle Registers.
0 = do not insert the Idle Code into this channel.
1 = insert the Idle Code into this channel.
NAME AND DESCRIPTION
MSB of the Idle Code.
LSB of the Idle Code.
TIDR4
CH12
CH20
CH28
26 of 44
CH4
TIDR3
CH11
CH19
CH27
CH3
TIDR2
CH10
CH18
CH26
CH2
TIDR1
CH17
CH25
CH1
CH9
(LSB)
DS2143/DS2143Q
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
TIDR0
(LSB)

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