DS2143QN Maxim Integrated Products, DS2143QN Datasheet - Page 19
![IC CONTROLLER E1 5V LP 44-PLCC](/photos/6/62/66291/175-44-plcc_sml.jpg)
DS2143QN
Manufacturer Part Number
DS2143QN
Description
IC CONTROLLER E1 5V LP 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2143Q.pdf
(44 pages)
Specifications of DS2143QN
Controller Type
E1 Controller
Interface
Parallel/Serial
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS2143QN+
Manufacturer:
Maxim Integrated Products
Quantity:
135
Company:
Part Number:
DS2143QN/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)
RMF
SYMBOL
RCMF
LORC
LOTC
RMF
TMF
RAF
SEC
TAF
RAF
POSITION
SR2.7
SR2.6
SR2.5
SR2.4
SR2.3
SR2.2
SR2.1
SR2.0
TMF
NAME AND DESCRIPTION
Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
Receive Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
One-Second Timer. Set on increments of 1 second based on
RCLK.
Transmit Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 s). Will force pin 34
high if enabled via TCR2.0. Based on RCLK.
Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 s (3 s ±1 s).
SEC
19 of 44
TAF
LOTC
RCMF
DS2143/DS2143Q
LORC
(LSB)