ISP1581BD-T ST-Ericsson Inc, ISP1581BD-T Datasheet - Page 47

• Manufacturer Part Number: ISP1581BD-T
• Description: IC USB CTRL HI-SPEED 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD-T

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 65:
10. Power supply
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Test Mode register: bit allocation
FORCEHS
R/W
9.5.5 Test Mode register (address: 84H)
7
0
0
Table 64:
This 1-byte register allows the firmware to set the (D , D
states for testing purposes. The bit allocation is given in
Remark: Only one bit can be set at a time.
Table 66:
[1]
[2]
The ISP1581 can be powered from 3.3 V or 5.0 V.
If the ISP1581 is powered from V
a 3.3 V supply voltage for the internal logic and the USB transceiver. For connection
details, see
The ISP1581 can also be operated from V
regulator is disabled and all the supply pins are connected to V
details see
Bit
15 to 8
7 to 0
Bit
7
6 to 5
4
3
2
1
0
[1]
[1]
[2]
[2]
[2]
[2]
R/W
Either FORCEHS or FORCEFS should be set to logic 1 at a time.
time.
Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set to logic 1 at a
6
-
-
reserved
Scratch Information register: bit description
Test Mode Register: bit description
Figure
Symbol
SFIRH[7:0]
SFIRL[7:0]
Symbol
FORCEHS
-
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
Figure
R/W
Rev. 06 — 23 December 2004
5
-
-
7.
6.
FORCEFS
Description
scratch firmware information register (high byte)
scratch firmware information register (low byte)
Description
A logic 1 forces the hardware to high-speed mode only and
disables the chirp detection logic.
reserved.
A logic 1 forces the physical layer to full-speed mode only and
disables the chirp detection logic.
A logic 1 sets the (D D ) lines to toggle in a pre-determined
random pattern.
Writing a logic 1 sets the (D D ) lines to the K state.
Writing a logic 1 sets the (D D ) lines to the J state.
Writing a logic 1 sets the (D D ) lines to a HS quiescent state.
The device only responds to a valid HS IN token with a NAK.
R/W
4
0
0
CC
= 5.0 V, an integrated voltage regulator provides
PRBS
R/W
3
0
0
CC
= 3.3 V. In this case, the internal
Hi-Speed USB peripheral controller
KSTATE
R/W
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
0
0
2
Table
lines to predetermined
65.
CC
JSTATE
R/W
. For connection
1
0
0
ISP1581
SE0_NAK
R/W
46 of 79
0
0
0