ISP1761ETUM ST-Ericsson Inc, ISP1761ETUM Datasheet - Page 108
ISP1761ETUM
Manufacturer Part Number
ISP1761ETUM
Description
IC USB CTRL HI-SPEED 128TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1761BEUM.pdf
(164 pages)
Specifications of ISP1761ETUM
Controller Type
USB Peripheral Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
ISP1761ET-T
ISP1761ET-T
ISP1761ET-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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NXP Semiconductors
Table 105. Debug register (address 0212h) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.5.4 Debug register
R/W
R/W
15
0
0
7
0
0
Table 103. Interrupt Configuration register (address 0210h) bit description
Table 104. Debug mode settings
[1]
This register can be accessed using address 0212h in 16-bit bus access mode or using
the upper-two bytes of the Interrupt Configuration register in 32-bit bus access mode. For
the bit allocation, see
Table 106. Debug register (address 0212h) bit allocation
Bit
7 to 6 CDBGMOD[1:0]
5 to 4 DDBGMODIN[1:0]
3 to 2 DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see
1
0
Value
00h
01h
1Xh
Bit
15 to 1
0
First NAK: The first NAK on an IN or OUT token after a previous ACK response.
R/W
R/W
Symbol
INTLVL
INTPOL
14
0
0
6
0
0
CDBGMOD
interrupt on all ACK and
NAK
interrupt on all ACK
interrupt on all ACK and
first NAK
Symbol
-
DEBUG
[1]
R/W
R/W
13
0
0
5
0
0
Table
Rev. 05 — 13 March 2008
Description
reserved
Always set this bit to logic 0 in both 16-bit and 32-bit accesses.
Description
Control 0 Debug Mode: For values, see
Data Debug Mode IN: For values, see
Interrupt Level: Selects signaling mode on output INT: 0 = level;
1 = pulsed. In pulsed mode, an interrupt produces a 60 ns pulse.
Bus reset value: unchanged.
Interrupt Polarity: Selects the signal polarity on output INT: 0 =
active LOW; 1 = active HIGH. Bus reset value: unchanged.
105.
reserved
R/W
R/W
12
0
0
4
0
0
DDBGMODIN
interrupt on all ACK and
NAK
interrupt on ACK
interrupt on all ACK and
first NAK
reserved
[1]
[1]
[1]
R/W
R/W
11
0
0
3
1
1
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
DDBGMODOUT
interrupt on all ACK, NYET and
NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET and
first NAK
Table 104
Table 104
Table 104
[1]
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
DEBUG
107 of 163
R/W
R/W
8
0
0
0
0
0
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