CY7C68300B-56LFXC Cypress Semiconductor Corp, CY7C68300B-56LFXC Datasheet - Page 9

• Manufacturer Part Number: CY7C68300B-56LFXC
• Description: IC USB 2.0 BRIDGE BULK 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68300B-56LFXC

• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5-1. AT2LP Pin Descriptions
Document 38-08033 Rev. *D
SSOP
N/A
N/A
N/A
N/A
N/A
N/A
56
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
QFN
36
36
13
54
N/A
N/A
N/A
N/A
N/A
56
32
33
34
35
37
38
39
40
41
42
43
44
45
46
47
48
49
Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode) (continued)
[3]
[3]
[3]
[3]
TQFP
70
100
66
67
68
69
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
[3]
(VBUS_PWR_VALID)
VBUS_ATA_ENABLE
DRVPWRVLD
GPIO2_nHS
Pin Name
ARESET#
(ATA_EN)
RESET#
INTRQ
GPIO0
GPIO1
GPIO3
GPIO4
GPIO5
(DA2)
DD10
DD12
CS0#
CS1#
DD11
GND
GND
GND
DA0
DA1
DA2
DD8
DD9
V
V
V
NC
NC
CC
CC
CC
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
PWR
PWR
PWR
Type
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
Pin
NC
NC
I
[1]
I
I
I
[1]
[1]
[1]
[1]
[3]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Default State
Driven HIGH
Driven HIGH
Driven HIGH
Driven HIGH
Driven HIGH
at Start-up
after 2 ms
after 2 ms
after 2 ms
after 2 ms
after 2 ms
delay
delay
delay
delay
delay
Input
Input
Input
Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
ATA Interrupt request.
ATA Address.
ATA Address.
Device Presence Detect (see section 5.3.5). Config-
urable polarity, controlled by EEPROM address 0x08.
This pin must be connected to GND if functionality is
not utilized.
Alternate Function: Input when the EEPROM config-
uration byte 8 has bit 7 set to one. The input value is
reported through EP1IN (byte 0, bit 0).
ATA Chip Select.
ATA Chip Select.
ATA Address.
ATA Reset.
Ground.
No Connect.
Chip Reset (see section 5.3.13). This pin is normally
tied to V
through a 0.1-µF capacitor, supplying a 10-ms reset.
V
VBUS detection (see section 5.3.9). Indicates to the
CY7C68300B/CY7C68301B that VBUS power is
present.
ATA Data bit 8.
ATA Data bit 9.
ATA Data bit 10.
ATA Data bit 11.
Ground.
V
No Connect.
General purpose I/O pins (see section 5.3.6). The
GPIO pins must be tied to GND if functionality is not
utilized. If the hs_indicator config bit is set, the
GPIO2_nHS pin will reflect the operating speed:
‘1’ = full-speed operation.
‘0’ = high-speed operation.
Ground.
ATA Data bit 12.
CC
CC
CC
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
CC
CY7C68300B/CY7C68301B
through a 100K resistor, and to GND
CY7C68320/CY7C68321
Pin Description
Page 9 of 36