DP83955AV National Semiconductor, DP83955AV Datasheet - Page 12

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

PROCESSOR BUS PINS
INTER-LERIC BUS PINS
STR
D(7 0)
DFS
BUFEN
WR
RD
MLOAD
ACKI
ACKO
IRD
Name
3 0 Pin Description
Pin
Driver
Type
TT
TT
TT
TT
TT
TT
TT
C
C
C
B Z
B Z
I O
O
O
O
O
I
I
I
I
Display Update STRobe This signal controls the latching of display data for network ports into the off
chip display latches
During processor access cycles (read or write is asserted) this signal is inactive (high)
Data Bus
Display Update Cycles These pins become outputs providing display data and port address
information
Processor Access Cycles Address input D(7 4) and Data input or output D(3 0) is performed via these
pins The read write and reset inputs control the direction of the signals
Note The data pins remain in their display update function (i e asserted as outputs) unless either the read or write
Display Frozen Strobe The assertion of the DFS signal active high at the end of the transmission of
each packet indicates that the status of that packet is frozen on the LEDs until the beginning of the next
received packet or for a maximum of 30 ms
BUFfer ENable This output controls the TRI-STATE operation of the bus transceiver which provides
the interface between the LERIC’s data pins and the processor’s data bus
Note The buffer enable output indicates the function of the data pins When it is high they are performing display update
WRite Strobe Strobe from the CPU used to write an internal register defined by the D(7 4) inputs
ReaD Strobe Strobe from the CPU used to read an internal register defined by the D(7 4) inputs
Device MLOAD and Reset When this input is low all of the RIC’s state machines and network ports are
reset and held inactive On the rising edge of MLOAD the logic levels present on the D(7 0) pins are
latched into the LERIC’s configuration registers The rising edge of MLOAD also signals the beginning
of the display test operation
ACKnowledge Input Input to the network ports’ arbitration chain
ACKnowledge Output Output from the network ports’ arbitration chain
Inter-LERIC Data When asserted as an output this signal provides a serial data stream in NRZ format
The signal is asserted by a LERIC when it is receiving data from one of its network segments The
default condition of this signal is to be an input In this state it may be driven by other devices on the
Inter-LERIC bus
strobe is asserted
cycles when it is low a processor access or MLOAD cycle is occurring
(Continued)
12
Description