DP8409AN-2 National Semiconductor, DP8409AN-2 Datasheet - Page 2
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DP8409AN-2
Manufacturer Part Number
DP8409AN-2
Description
IC CONTROLLER DYNAMIC RAM 68PLCC
Manufacturer
National Semiconductor
Datasheet
1.DP8409AN.pdf
(24 pages)
Specifications of DP8409AN-2
Controller Type
Dynamic RAM (DRAM) Controller, Drivers
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
250mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
48-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP8409AN-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP8409AN-2
Manufacturer:
NS
Quantity:
6 245
Part Number:
DP8409AN-2
Manufacturer:
NS/国半
Quantity:
20 000
Block and Connection Diagrams
Pin Definitions
V
have been assigned to the center of the package to reduce
voltage drops both DC and AC There are also two ground
pins to reduce the low level noise The second ground pin is
located two pins from V
can be inserted directly next to these pins It is important to
adequately decouple this device due to the high switching
currents that will occur when all 9 address bits change in the
same direction simultaneously A recommended solution
would be a 1 F multilayer ceramic capacitor in parallel with
a low-voltage tantalum capacitor both connected as close
as possible to pins 36 and 38 to reduce lead inductance
See figure below
Capacitor values should be chosen depending on the particular application
CC
GND GND V
See NS Package Number D48A N48A or V68A
Order Number DP8409AD DP8409AN
DP8409AN-3 or DP8409AV-2
CC
e
CC
5V
so that decoupling capacitors
g
5% The three supply pins
TL F 8409–4
TL F 8409 – 2
2
R0 – R8 Row Address Inputs
C0– C8 Column Address Inputs
Q0– Q8 Multiplexed Address Outputs Selected from
the Row Address Input Latch the Column Address Input
Latch or the Refresh Counter
RASIN Row Address Strobe Input Enables selected
RAS
when RFSH is low
R C (RFCK) In Auto-Refresh Mode this pin is the exter-
nal Refresh Clock Input one refresh cycle has to be per-
formed each clock period In all other modes it is Row Col-
umn Select Input selects either the row or column address
input latch onto the output bus
n
output when M2 (RFSH) is high or all RAS
Dual-In-Line Package
68 Pin PCC
Top View
TL F 8409– 3
TL F 8409– 5
n
outputs