DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 57

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

15 0 AC Timing Parameters DP8520A DP8521A DP8522A
Unless otherwise stated V
per bank including trace capacitance (see Note 2)
Two different loads are specified
C
C
Note 1 ‘‘Absolute Maximum Ratings’’ are the values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device
should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation
Note 2 Input pulse 0V to 3V tR
Note 3 AC Production testing is done at 50 pF
Number
500
501
502
503
504
505
506
600
601
602
603
604
605
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 and 10 or
tHMLADD
tSADDML
tWML
tSADAQML
tHADAQML
tSCSARQ
tSMLARQ
tSCKVSRL
tHVSRLCK
tSCKAVSRL
tPVSRLDTL
tPVSRLDTH
tPCKDTL
Symbol
CC
e
tF
e
e
5 0V
2 5 ns Input reference point on AC measurements is 1 5V Output reference points are 2 4V for High and 0 8V for Low
Mode Address Held from ML Negated
Mode Address Setup to ML Negated
ML Pulse Width
Mode Address Setup to AREQ Asserted
Mode Address Held from AREQ Asserted
CS Asserted Setup to
AREQ Asserted
ML Asserted Setup to AREQ Asserted
VSRL Low Setup to CLK Rising Edge to
guarantee counting VSRL as being Low
(used to determine when to end Graphics
Shift load access)
VSRL Low from CLK High (to guarantee
VSRL is not counted as being Low until
the next rising clock edge)
AVSRLRQ Low before CLK Rising Edge
to guarantee locking the VRAM to only
Port A accesses
VSRL Low to DT OE Low during
Graphics Shift Register Load access
VSRL Negated to DT OE Negated
CLK to DT OE Negated
g
10% 0 C
Parameter Description
Programing
k
T
A k
70 C the output load capacitance is typical for 4 banks of 18 VRAMs
57
C
C
C
H
H
H
e
e
e
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 and 10
Min
15
38
10
12
7
6
0
6
7
3
C
L
8520A 21A 22A-25
Max
(Continued)
23
22
27
Min
15
38
10
12
7
6
0
6
7
3
C
H
Max
33
32
37