DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 7
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DP83953VUL
Manufacturer Part Number
DP83953VUL
Description
IC CTRLR RIC REPEATER 160-PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83953VUL.pdf
(90 pages)
Specifications of DP83953VUL
Controller Type
Ethernet Repeater Interface Controller
Interface
IEEE 802.3
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
870mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83953VUL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83953VUL
Manufacturer:
HJC
Quantity:
2 010
Company:
Part Number:
DP83953VUL
Manufacturer:
Texas Instruments
Quantity:
10 000
2.0 Pin Descriptions
TT = TTL compatible, B = Bi-directional, C = CMOS compatible, OD = Open Drain, I = Input, O = Output,
Z = high impedance
RTI
CDEC
WR
RD
MLOAD
67
91
90
89
92
(Continued)
TT
TT
TT
TT
C
O
I
I
I
I
REAL TIME INTERRUPT: A low level on the RTI output indi-
cates the RIC2A's real time (packet specific) interrupt logic re-
quires CPU attention. The interrupt is cleared by reading the
Real Time Interrupt Status register. All interrupt sources may be
masked.
COUNTER DECREMENT: A rising edge on the CDEC input
strobe decrements all of the RIC2A's Port Event Counters by
one. This input is internally synchronized and if necessary the
operation of the signal is delayed if there is a simultaneous in-
ternally generated counting operation.
WRITE STROBE: Strobe from the CPU used to write an internal
register defined by the RA0 - RA4 inputs.
READ STROBE: Strobe from the CPU used to read an internal
register defined by the RA0 - RA4 inputs.
DEVICE RESET AND MODE LOAD: When this input cycles
back up from low to high, all of the RIC2A's state machines,
counters and network ports are reset and held inactive. On the
rising edge of MLOAD the logic levels present on the D0 - 7 pins
and RA0 - RA4 inputs are latched into the RIC2A's configuration
registers. The rising edge of MLOAD also signals the beginning
of the display test operation. The clock signal must be present
on the CLKIN pin during MLOAD assertion and de-assertion.
7
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