XCCACE-TQ144I Xilinx Inc, XCCACE-TQ144I Datasheet - Page 49

• Manufacturer Part Number: XCCACE-TQ144I
• Description: IC ACE CONTROLLER CHIP
• Manufacturer: Xilinx Inc

Specifications of XCCACE-TQ144I

• Controller Type: ACE Controller
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 30mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -

Once the CompactFlash device is ready to receive a new
command, the following information needs to be written to
the MPU interface:
1. The sector address or logical block address (LBA) of
2. The number of sectors that will be written should be
3. The WriteMemCardData command (04h) should be
DS080 (v2.0) October 1, 2008
Product Specification
the first sector to be transferred should be written to the
following MPU address locations:
-
-
-
-
loaded into the low byte of the SECCNTCMDREG
register (MPU byte address 14h)
written to the high byte of the SECCNTCMDREG
register (MPU byte address 15h)
LBA[7:0] @ MPU byte address 10h
LBA[15:8] @ MPU byte address 11h
LBA[23:16] @ MPU byte address 12h
LBA[27:24] @ MPU byte address 13h (note that
only four bits are used in the most significant LBA
byte)
R
No
Wait for Buffer Ready
Write Data Buffer
Figure 29: Write Data Buffer Control Flow Process
Decrement Data
Buffer is written.
Return success.
Write data word
Count variable*
Count variable
Initialize Data
Data Count
equal to 0?
to buffer
Yes
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*Set Data Count variable equal to
the number of data items in a buffer
(e.g., 16 bytes or 32 words)
Write data bits 7:0 to byte address 40h
Write data bits 15:8 to byte address 41h
(Note that the following conditions must
be valid for a data write to occur to the
CompactFlash data buffer:
1. The data buffer must be ready
2. A single write to byte address 41h
must occur that will cause the entire 16-
bit data register to be written to the
buffer)
4. Reset the CFGJTAG controller by setting the
Immediately after writing the command to the MPU inter-
face, the CFGJTAG controller should be reset before writing
the sector data to the data buffer.
The control flow process for writing the sector data from the
data buffer is shown in
After all of the required sector data has been written, the
CFGJTAG controller should be taken out of reset and the
CompactFlash lock should be released. This is done by set-
ting the CFGRESET (bit 7) and LOCKREQ (bit 1) bits of the
low byte of the CONTROLREG register (MPU byte address
18h) to a 0, respectively. Note that all requested sector data
should be written to the data buffer in order to avoid a dead-
lock situation with the CompactFlash device.
CFGRESET bit (bit 7) of the CONTROLREG register
(MPU address 18h) to a 1.
System ACE CompactFlash Solution
DS080_54_051701
Figure
29.
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