AD9956YCPZ Analog Devices Inc, AD9956YCPZ Datasheet - Page 22

• Manufacturer Part Number: AD9956YCPZ
• Description: IC SYNTHESIZER 1.8V 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9956YCPZ

• Resolution (bits): 14 b
• Master Fclk: 3GHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Transmitting Current: 85mA
• Modulation Type: FSK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +125°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9956-VCO/PCBZ - BOARD EVAL 14BIT 1.8V 48LFCSPAD9956/PCBZ - BOARD EVAL FOR AD9956
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9956
SERIAL PORT OPERATION
An AD9956 serial data-port communication cycle has two
phases. Phase 1 is the instruction cycle, which is the writing of
an instruction byte to the AD9956, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9956 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the
register being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9956. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9956
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
SCLK
SDI/O
SCLK
SDI/O
SCLK
SDI/O
SCLK
SDI/O
SDO
CS
CS
CS
CS
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INSTRUCTION CYCLE
Figure 32. 2-Wire Serial Port Read Timing—Clock Stall High
INSTRUCTION CYCLE
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INSTRUCTION CYCLE
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INSTRUCTION CYCLE
Figure 30. 3-Wire Serial Port Read Timing—Clock Stall Low
5
5
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Figure 31. Serial Port Write Timing—Clock Stall High
Figure 29. Serial Port Write Timing—Clock Stall Low
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register being accessed. For example, when accessing Control
Function Register 2, which is four bytes wide, Phase 2 requires that
four bytes be transferred. If accessing a frequency tuning word,
which is six bytes wide, Phase 2 requires that six bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9956
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9956 is registered on the rising edge of
SCLK. All data is driven out of the AD9956 on the falling edge
of SCLK. Figure 29 through Figure 32 are useful in understand-
ing the general operation of the AD9956 serial port.
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DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
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DON'T CARE
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